;; Function compute_jump_reg_dependencies (_ZL29compute_jump_reg_dependenciesP7rtx_defP11bitmap_head, funcdef_no=2456, decl_uid=99321, cgraph_uid=1504, symbol_order=1551) starting the processing of deferred insns ending the processing of deferred insns df_analyze called starting the processing of deferred insns ending the processing of deferred insns compute_jump_reg_dependencies Dataflow summary: ;; fully invalidated by EH 0 [0] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [0] 65 [1] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 78 [14] 79 [15] 80 [16] 81 [17] 82 [18] 83 [19] 96 [lr] 97 [ctr] 98 [ca] 100 [0] 101 [1] 105 [5] 106 [6] 107 [7] 109 [vscr] ;; hardware regs used 1 [1] 2 [2] 99 [ap] 109 [vscr] 110 [sfp] ;; regular block artificial uses 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] ;; eh block artificial uses 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] ;; entry block defs 1 [1] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 31 [31] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 96 [lr] 99 [ap] 109 [vscr] 110 [sfp] ;; exit block uses 1 [1] 2 [2] 31 [31] 108 [vrsave] 109 [vscr] 110 [sfp] ;; regs ever live ;; ref usage r1={1d,2u} r2={1d,2u} r3={1d} r4={1d} r5={1d} r6={1d} r7={1d} r8={1d} r9={1d} r10={1d} r31={1d,2u} r33={1d} r34={1d} r35={1d} r36={1d} r37={1d} r38={1d} r39={1d} r40={1d} r41={1d} r42={1d} r43={1d} r44={1d} r45={1d} r66={1d} r67={1d} r68={1d} r69={1d} r70={1d} r71={1d} r72={1d} r73={1d} r74={1d} r75={1d} r76={1d} r77={1d} r96={1d} r99={1d,1u} r108={1u} r109={1d,1u} r110={1d,2u} ;; total ref usage 51{40d,11u,0e} in 0{0 regular + 0 call} insns. ;; basic block 2, loop depth 0, count 1073741824 (estimated locally), maybe hot ;; prev block 0, next block 1, flags: (REACHABLE, RTL, MODIFIED) ;; pred: ENTRY [always] count:1073741824 (estimated locally) (FALLTHRU) ;; bb 2 artificial_defs: { } ;; bb 2 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] ;; lr def ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] ;; live gen ;; live kill (note 5 0 4 2 [bb 2] NOTE_INSN_BASIC_BLOCK) (note 4 5 0 2 NOTE_INSN_FUNCTION_BEG) ;; succ: EXIT [always] count:1073741824 (estimated locally) (FALLTHRU) /builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc:260:1 ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] ;; Function update_node_sched_params (_ZL24update_node_sched_paramsiiii, funcdef_no=2466, decl_uid=99701, cgraph_uid=1514, symbol_order=1565) scanning new insn with uid = 102. rescanning insn with uid = 2. scanning new insn with uid = 103. rescanning insn with uid = 3. scanning new insn with uid = 104. rescanning insn with uid = 4. scanning new insn with uid = 105. rescanning insn with uid = 5. starting the processing of deferred insns ending the processing of deferred insns df_analyze called df_worklist_dataflow_doublequeue: n_basic_blocks 8 n_edges 9 count 8 ( 1) update_node_sched_params Dataflow summary: def_info->table_size = 68, use_info->table_size = 0 ;; fully invalidated by EH 0 [0] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [0] 65 [1] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 78 [14] 79 [15] 80 [16] 81 [17] 82 [18] 83 [19] 96 [lr] 97 [ctr] 98 [ca] 100 [0] 101 [1] 105 [5] 106 [6] 107 [7] 109 [vscr] ;; hardware regs used 1 [1] 2 [2] 99 [ap] 109 [vscr] 110 [sfp] ;; regular block artificial uses 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] ;; eh block artificial uses 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] ;; entry block defs 1 [1] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 31 [31] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 96 [lr] 99 [ap] 109 [vscr] 110 [sfp] ;; exit block uses 1 [1] 2 [2] 31 [31] 108 [vrsave] 109 [vscr] 110 [sfp] ;; regs ever live 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] ;; ref usage r1={1d,7u} r2={1d,8u} r3={1d,1u} r4={1d,1u} r5={1d,1u} r6={1d,1u} r7={1d} r8={1d} r9={1d} r10={1d} r31={1d,7u} r33={1d} r34={1d} r35={1d} r36={1d} r37={1d} r38={1d} r39={1d} r40={1d} r41={1d} r42={1d} r43={1d} r44={1d} r45={1d} r66={1d} r67={1d} r68={1d} r69={1d} r70={1d} r71={1d} r72={1d} r73={1d} r74={1d} r75={1d} r76={1d} r77={1d} r96={1d} r99={1d,6u} r108={1u} r109={1d,1u} r110={1d,7u} r118={1d,3u} r119={1d,1u} r120={1d,1u} r121={1d,1u} r122={1d,1u} r123={1d,1u} r124={1d,1u} r125={2d,1u} r126={1d,1u} r127={1d,1u} r128={1d,3u} r129={1d,1u} r130={1d,2u} r131={1d,3u} r132={1d,1u} r133={1d,2u} r134={1d,2u} r135={1d,1u} r136={1d,2u} r137={1d,3u} r138={1d,11u} r139={1d,6u} r140={1d,1u} r149={1d,1u} r151={1d,1u} r153={1d,1u} r154={1d,1u} r157={1d,1u} r158={1d,1u} r159={1d,1u} r160={1d,1u} ;; total ref usage 171{72d,99u,0e} in 68{68 regular + 0 call} insns. ( )->[0]->( 2 ) ;; bb 0 artificial_defs: { d0(1){ }d1(2){ }d2(3){ }d3(4){ }d4(5){ }d5(6){ }d6(7){ }d7(8){ }d8(9){ }d9(10){ }d10(31){ }d11(33){ }d12(34){ }d13(35){ }d14(36){ }d15(37){ }d16(38){ }d17(39){ }d18(40){ }d19(41){ }d20(42){ }d21(43){ }d22(44){ }d23(45){ }d24(66){ }d25(67){ }d26(68){ }d27(69){ }d28(70){ }d29(71){ }d30(72){ }d31(73){ }d32(74){ }d33(75){ }d34(76){ }d35(77){ }d36(96){ }d37(99){ }d38(109){ }d39(110){ }} ;; bb 0 artificial_uses: { } ;; lr in 108 [vrsave] ;; lr use ;; lr def 1 [1] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 31 [31] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 96 [lr] 99 [ap] 109 [vscr] 110 [sfp] ;; live in ;; live gen 1 [1] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 31 [31] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 96 [lr] 99 [ap] 109 [vscr] 110 [sfp] ;; live kill ;; lr out 1 [1] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] ;; live out 1 [1] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] ( 0 )->[2]->( 3 4 ) ;; bb 2 artificial_defs: { } ;; bb 2 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] ;; lr use 1 [1] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 31 [31] 99 [ap] 110 [sfp] ;; lr def 118 126 128 129 131 132 133 135 136 137 138 139 140 149 151 153 157 158 159 160 ;; live in 1 [1] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] ;; live gen 118 126 128 129 131 132 133 135 136 137 138 139 140 149 151 153 ;; live kill ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 128 136 138 139 ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 128 136 138 139 ( 2 )->[3]->( 5 ) ;; bb 3 artificial_defs: { } ;; bb 3 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 128 136 138 139 ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 118 128 138 ;; lr def 127 ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 128 136 138 139 ;; live gen 127 ;; live kill ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 128 136 138 139 ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 128 136 138 139 ( 2 )->[4]->( 5 6 ) ;; bb 4 artificial_defs: { } ;; bb 4 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 128 136 138 139 ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 118 128 139 ;; lr def 154 ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 128 136 138 139 ;; live gen 154 ;; live kill ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 128 136 138 139 ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 128 136 138 139 ( 4 3 )->[5]->( 7 ) ;; bb 5 artificial_defs: { } ;; bb 5 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 128 136 138 139 ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 136 138 139 ;; lr def 119 120 125 134 ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 128 136 138 139 ;; live gen 119 120 125 134 ;; live kill ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 125 128 ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 125 128 ( 4 )->[6]->( 7 ) ;; bb 6 artificial_defs: { } ;; bb 6 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 128 136 138 139 ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 136 138 139 ;; lr def 121 122 123 124 125 130 ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 128 136 138 139 ;; live gen 121 122 123 124 125 130 ;; live kill ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 125 128 ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 125 128 ( 5 6 )->[7]->( 1 ) ;; bb 7 artificial_defs: { } ;; bb 7 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 125 128 ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 125 128 ;; lr def ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 125 128 ;; live gen ;; live kill ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] ( 7 )->[1]->( ) ;; bb 1 artificial_defs: { } ;; bb 1 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(108){ }u-1(109){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 108 [vrsave] 109 [vscr] 110 [sfp] ;; lr use 1 [1] 2 [2] 31 [31] 108 [vrsave] 109 [vscr] 110 [sfp] ;; lr def ;; live in 1 [1] 2 [2] 31 [31] 109 [vscr] 110 [sfp] ;; live gen ;; live kill ;; lr out ;; live out Finding needed instructions: Adding insn 45 to worklist Adding insn 29 to worklist Adding insn 48 to worklist Adding insn 67 to worklist Adding insn 58 to worklist Adding insn 94 to worklist Finished finding needed instructions: processing block 7 lr out = 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] processing block 5 lr out = 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 125 128 Adding insn 77 to worklist Adding insn 74 to worklist Adding insn 72 to worklist Adding insn 71 to worklist processing block 3 lr out = 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 128 136 138 139 Adding insn 47 to worklist processing block 6 lr out = 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 125 128 Adding insn 91 to worklist Adding insn 90 to worklist Adding insn 87 to worklist Adding insn 85 to worklist Adding insn 84 to worklist Adding insn 83 to worklist processing block 4 lr out = 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 128 136 138 139 Adding insn 66 to worklist processing block 2 lr out = 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 128 136 138 139 Adding insn 44 to worklist Adding insn 41 to worklist Adding insn 39 to worklist Adding insn 38 to worklist Adding insn 37 to worklist Adding insn 36 to worklist Adding insn 35 to worklist Adding insn 24 to worklist Adding insn 23 to worklist Adding insn 22 to worklist Adding insn 21 to worklist Adding insn 17 to worklist Adding insn 5 to worklist Adding insn 105 to worklist Adding insn 4 to worklist Adding insn 104 to worklist Adding insn 3 to worklist Adding insn 103 to worklist Adding insn 2 to worklist Adding insn 102 to worklist df_worklist_dataflow_doublequeue: n_basic_blocks 8 n_edges 9 count 8 ( 1) insn_cost 4 for 102: r157:DI=%3:DI REG_DEAD %3:DI insn_cost 4 for 2: r137:DI=r157:DI REG_DEAD r157:DI insn_cost 4 for 103: r158:DI=%4:DI REG_DEAD %4:DI insn_cost 4 for 3: r138:DI=r158:DI REG_DEAD r158:DI insn_cost 4 for 104: r159:DI=%5:DI REG_DEAD %5:DI insn_cost 4 for 4: r139:DI=r159:DI REG_DEAD r159:DI insn_cost 4 for 105: r160:DI=%6:DI REG_DEAD %6:DI insn_cost 4 for 5: r140:DI=r160:DI REG_DEAD r160:DI insn_cost 0 for 9: debug begin stmt marker insn_cost 0 for 10: debug begin stmt marker insn_cost 0 for 11: debug begin stmt marker insn_cost 0 for 13: debug this => `_ZL20node_sched_param_vec' insn_cost 0 for 14: debug ix => r137:DI#0 insn_cost 0 for 15: debug inline entry marker insn_cost 8 for 17: r131:DI=[unspec[`*.LANCHOR0',%2:DI] 47] insn_cost 0 for 18: debug this => r131:DI insn_cost 0 for 19: debug ix => r137:DI#0 insn_cost 0 for 20: debug inline entry marker insn_cost 4 for 21: r129:DI=zero_extend(r137:DI#0) REG_DEAD r137:DI insn_cost 4 for 22: r135:DI=r129:DI<<0x4 REG_DEAD r129:DI insn_cost 4 for 23: r133:DI=r135:DI+0x8 REG_DEAD r135:DI insn_cost 4 for 24: r128:DI=r131:DI+r133:DI insn_cost 0 for 25: debug this => optimized away insn_cost 0 for 26: debug ix => optimized away insn_cost 0 for 27: debug this => optimized away insn_cost 0 for 28: debug ix => optimized away insn_cost 4 for 29: [r131:DI+r133:DI]=r139:DI#0 REG_DEAD r133:DI REG_DEAD r131:DI insn_cost 0 for 30: debug begin stmt marker insn_cost 76 for 35: r149:SI=r139:DI#0/r138:DI#0 insn_cost 12 for 36: r151:SI=r149:SI*r138:DI#0 REG_DEAD r149:SI insn_cost 4 for 37: r118:SI=r139:DI#0-r151:SI REG_DEAD r151:SI insn_cost 4 for 38: r126:SI=r138:DI#0-r140:DI#0 REG_DEAD r140:DI insn_cost 4 for 39: r132:SI=r126:SI-0x1 REG_DEAD r126:SI insn_cost 76 for 41: r136:SI=r132:SI/r138:DI#0 REG_DEAD r132:SI insn_cost 4 for 44: r153:CC=cmp(r118:SI,0) insn_cost 8 for 45: pc={(r153:CC>=0)?L56:pc} REG_DEAD r153:CC REG_BR_PROB 633507684 insn_cost 4 for 47: r127:SI=r118:SI+r138:DI#0 REG_DEAD r118:SI insn_cost 4 for 48: [r128:DI+0x4]=r127:SI REG_DEAD r127:SI insn_cost 0 for 49: debug begin stmt marker insn_cost 0 for 50: debug D#58 => optimized away insn_cost 0 for 51: debug D#57 => D#58-0x1 insn_cost 0 for 52: debug sc_until_cycle_zero => D#57/r138:DI#0 insn_cost 0 for 53: debug begin stmt marker insn_cost 4 for 58: [r128:DI+0x4]=r118:SI REG_DEAD r118:SI insn_cost 0 for 59: debug begin stmt marker insn_cost 0 for 60: debug D#60 => optimized away insn_cost 0 for 61: debug D#59 => D#60-0x1 insn_cost 0 for 62: debug sc_until_cycle_zero => D#59/r138:DI#0 insn_cost 0 for 63: debug begin stmt marker insn_cost 4 for 66: r154:CC=cmp(r139:DI#0,0) insn_cost 8 for 67: pc={(r154:CC>=0)?L80:pc} REG_DEAD r154:CC REG_BR_PROB 914812532 insn_cost 0 for 70: debug begin stmt marker insn_cost 4 for 71: r119:SI=r138:DI#0-r139:DI#0 REG_DEAD r139:DI insn_cost 4 for 72: r120:SI=r119:SI-0x1 REG_DEAD r119:SI insn_cost 76 for 74: r134:SI=r120:SI/r138:DI#0 REG_DEAD r138:DI REG_DEAD r120:SI insn_cost 0 for 75: debug stage => r134:SI insn_cost 0 for 76: debug begin stmt marker insn_cost 4 for 77: r125:SI=r136:SI-r134:SI REG_DEAD r136:SI REG_DEAD r134:SI insn_cost 0 for 82: debug begin stmt marker insn_cost 4 for 83: r121:SI=r139:DI#0+0x1 REG_DEAD r139:DI insn_cost 4 for 84: r122:SI=r121:SI+r138:DI#0 REG_DEAD r121:SI insn_cost 4 for 85: r123:SI=r122:SI-0x1 REG_DEAD r122:SI insn_cost 76 for 87: r130:SI=r123:SI/r138:DI#0 REG_DEAD r138:DI REG_DEAD r123:SI insn_cost 0 for 88: debug stage => r130:SI insn_cost 0 for 89: debug begin stmt marker insn_cost 4 for 90: r124:SI=r130:SI+r136:SI REG_DEAD r136:SI REG_DEAD r130:SI insn_cost 4 for 91: r125:SI=r124:SI-0x1 REG_DEAD r124:SI insn_cost 4 for 94: [r128:DI+0x8]=r125:SI REG_DEAD r128:DI REG_DEAD r125:SI Trying 2 -> 21: 2: r137:DI=r157:DI REG_DEAD r157:DI 21: r129:DI=zero_extend(r137:DI#0) REG_DEAD r137:DI Successfully matched this instruction: (set (reg:DI 129 [ _25 ]) (zero_extend:DI (subreg:SI (reg:DI 157) 0))) allowing combination of insns 2 and 21 original costs 4 + 4 = 8 replacement cost 4 deferring rescan insn with uid = 14. deferring rescan insn with uid = 19. deferring deletion of insn with uid = 2. modifying insn i3 21: r129:DI=zero_extend(r157:DI#0) REG_DEAD r157:DI deferring rescan insn with uid = 21. Trying 21 -> 22: 21: r129:DI=zero_extend(r157:DI#0) REG_DEAD r157:DI 22: r135:DI=r129:DI<<0x4 REG_DEAD r129:DI Successfully matched this instruction: (set (reg:DI 135 [ _31 ]) (and:DI (ashift:DI (reg:DI 157) (const_int 4 [0x4])) (const_int 68719476720 [0xffffffff0]))) allowing combination of insns 21 and 22 original costs 4 + 4 = 8 replacement cost 4 deferring deletion of insn with uid = 21. modifying insn i3 22: r135:DI=r157:DI<<0x4&0xffffffff0 REG_DEAD r157:DI deferring rescan insn with uid = 22. Trying 22 -> 23: 22: r135:DI=r157:DI<<0x4&0xffffffff0 REG_DEAD r157:DI 23: r133:DI=r135:DI+0x8 REG_DEAD r135:DI Failed to match this instruction: (set (reg:DI 133 [ _29 ]) (plus:DI (and:DI (ashift:DI (reg:DI 157) (const_int 4 [0x4])) (const_int 68719476720 [0xffffffff0])) (const_int 8 [0x8]))) Trying 17 -> 24: 17: r131:DI=[unspec[`*.LANCHOR0',%2:DI] 47] 24: r128:DI=r131:DI+r133:DI Failed to match this instruction: (parallel [ (set (reg/f:DI 128 [ _24 ]) (plus:DI (mem/f/c:DI (unspec:DI [ (symbol_ref:DI ("*.LANCHOR0") [flags 0x182]) (reg:DI 2 2) ] UNSPEC_TOCREL) [91 node_sched_param_vec.m_vec+0 S8 A64]) (reg:DI 133 [ _29 ]))) (set (reg/f:DI 131 [ _27 ]) (mem/f/c:DI (unspec:DI [ (symbol_ref:DI ("*.LANCHOR0") [flags 0x182]) (reg:DI 2 2) ] UNSPEC_TOCREL) [91 node_sched_param_vec.m_vec+0 S8 A64])) ]) Failed to match this instruction: (parallel [ (set (reg/f:DI 128 [ _24 ]) (plus:DI (mem/f/c:DI (unspec:DI [ (symbol_ref:DI ("*.LANCHOR0") [flags 0x182]) (reg:DI 2 2) ] UNSPEC_TOCREL) [91 node_sched_param_vec.m_vec+0 S8 A64]) (reg:DI 133 [ _29 ]))) (set (reg/f:DI 131 [ _27 ]) (mem/f/c:DI (unspec:DI [ (symbol_ref:DI ("*.LANCHOR0") [flags 0x182]) (reg:DI 2 2) ] UNSPEC_TOCREL) [91 node_sched_param_vec.m_vec+0 S8 A64])) ]) Trying 23 -> 24: 23: r133:DI=r135:DI+0x8 REG_DEAD r135:DI 24: r128:DI=r131:DI+r133:DI Failed to match this instruction: (parallel [ (set (reg/f:DI 128 [ _24 ]) (plus:DI (plus:DI (reg/f:DI 131 [ _27 ]) (reg:DI 135 [ _31 ])) (const_int 8 [0x8]))) (set (reg:DI 133 [ _29 ]) (plus:DI (reg:DI 135 [ _31 ]) (const_int 8 [0x8]))) ]) Failed to match this instruction: (parallel [ (set (reg/f:DI 128 [ _24 ]) (plus:DI (plus:DI (reg/f:DI 131 [ _27 ]) (reg:DI 135 [ _31 ])) (const_int 8 [0x8]))) (set (reg:DI 133 [ _29 ]) (plus:DI (reg:DI 135 [ _31 ]) (const_int 8 [0x8]))) ]) Successfully matched this instruction: (set (reg:DI 133 [ _29 ]) (plus:DI (reg:DI 135 [ _31 ]) (const_int 8 [0x8]))) Failed to match this instruction: (set (reg/f:DI 128 [ _24 ]) (plus:DI (plus:DI (reg/f:DI 131 [ _27 ]) (reg:DI 135 [ _31 ])) (const_int 8 [0x8]))) Trying 22, 23 -> 24: 22: r135:DI=r157:DI<<0x4&0xffffffff0 REG_DEAD r157:DI 23: r133:DI=r135:DI+0x8 REG_DEAD r135:DI 24: r128:DI=r131:DI+r133:DI Failed to match this instruction: (parallel [ (set (reg/f:DI 128 [ _24 ]) (plus:DI (plus:DI (and:DI (ashift:DI (reg:DI 157) (const_int 4 [0x4])) (const_int 68719476720 [0xffffffff0])) (reg/f:DI 131 [ _27 ])) (const_int 8 [0x8]))) (set (reg:DI 133 [ _29 ]) (plus:DI (and:DI (ashift:DI (reg:DI 157) (const_int 4 [0x4])) (const_int 68719476720 [0xffffffff0])) (const_int 8 [0x8]))) ]) Failed to match this instruction: (parallel [ (set (reg/f:DI 128 [ _24 ]) (plus:DI (plus:DI (and:DI (ashift:DI (reg:DI 157) (const_int 4 [0x4])) (const_int 68719476720 [0xffffffff0])) (reg/f:DI 131 [ _27 ])) (const_int 8 [0x8]))) (set (reg:DI 133 [ _29 ]) (plus:DI (and:DI (ashift:DI (reg:DI 157) (const_int 4 [0x4])) (const_int 68719476720 [0xffffffff0])) (const_int 8 [0x8]))) ]) Failed to match this instruction: (set (reg:DI 133 [ _29 ]) (plus:DI (and:DI (ashift:DI (reg:DI 157) (const_int 4 [0x4])) (const_int 68719476720 [0xffffffff0])) (const_int 8 [0x8]))) Trying 23, 17 -> 24: 23: r133:DI=r135:DI+0x8 REG_DEAD r135:DI 17: r131:DI=[unspec[`*.LANCHOR0',%2:DI] 47] 24: r128:DI=r131:DI+r133:DI Failed to match this instruction: (parallel [ (set (reg/f:DI 128 [ _24 ]) (plus:DI (plus:DI (mem/f/c:DI (unspec:DI [ (symbol_ref:DI ("*.LANCHOR0") [flags 0x182]) (reg:DI 2 2) ] UNSPEC_TOCREL) [91 node_sched_param_vec.m_vec+0 S8 A64]) (reg:DI 135 [ _31 ])) (const_int 8 [0x8]))) (set (reg:DI 133 [ _29 ]) (plus:DI (reg:DI 135 [ _31 ]) (const_int 8 [0x8]))) (set (reg/f:DI 131 [ _27 ]) (mem/f/c:DI (unspec:DI [ (symbol_ref:DI ("*.LANCHOR0") [flags 0x182]) (reg:DI 2 2) ] UNSPEC_TOCREL) [91 node_sched_param_vec.m_vec+0 S8 A64])) ]) Failed to match this instruction: (parallel [ (set (reg/f:DI 128 [ _24 ]) (plus:DI (plus:DI (mem/f/c:DI (unspec:DI [ (symbol_ref:DI ("*.LANCHOR0") [flags 0x182]) (reg:DI 2 2) ] UNSPEC_TOCREL) [91 node_sched_param_vec.m_vec+0 S8 A64]) (reg:DI 135 [ _31 ])) (const_int 8 [0x8]))) (set (reg:DI 133 [ _29 ]) (plus:DI (reg:DI 135 [ _31 ]) (const_int 8 [0x8]))) (set (reg/f:DI 131 [ _27 ]) (mem/f/c:DI (unspec:DI [ (symbol_ref:DI ("*.LANCHOR0") [flags 0x182]) (reg:DI 2 2) ] UNSPEC_TOCREL) [91 node_sched_param_vec.m_vec+0 S8 A64])) ]) Trying 22, 23, 17 -> 24: 22: r135:DI=r157:DI<<0x4&0xffffffff0 REG_DEAD r157:DI 23: r133:DI=r135:DI+0x8 REG_DEAD r135:DI 17: r131:DI=[unspec[`*.LANCHOR0',%2:DI] 47] 24: r128:DI=r131:DI+r133:DI Failed to match this instruction: (parallel [ (set (reg/f:DI 128 [ _24 ]) (plus:DI (plus:DI (and:DI (ashift:DI (reg:DI 157) (const_int 4 [0x4])) (const_int 68719476720 [0xffffffff0])) (mem/f/c:DI (unspec:DI [ (symbol_ref:DI ("*.LANCHOR0") [flags 0x182]) (reg:DI 2 2) ] UNSPEC_TOCREL) [91 node_sched_param_vec.m_vec+0 S8 A64])) (const_int 8 [0x8]))) (set (reg:DI 133 [ _29 ]) (plus:DI (and:DI (ashift:DI (reg:DI 157) (const_int 4 [0x4])) (const_int 68719476720 [0xffffffff0])) (const_int 8 [0x8]))) (set (reg/f:DI 131 [ _27 ]) (mem/f/c:DI (unspec:DI [ (symbol_ref:DI ("*.LANCHOR0") [flags 0x182]) (reg:DI 2 2) ] UNSPEC_TOCREL) [91 node_sched_param_vec.m_vec+0 S8 A64])) ]) Failed to match this instruction: (parallel [ (set (reg/f:DI 128 [ _24 ]) (plus:DI (plus:DI (and:DI (ashift:DI (reg:DI 157) (const_int 4 [0x4])) (const_int 68719476720 [0xffffffff0])) (mem/f/c:DI (unspec:DI [ (symbol_ref:DI ("*.LANCHOR0") [flags 0x182]) (reg:DI 2 2) ] UNSPEC_TOCREL) [91 node_sched_param_vec.m_vec+0 S8 A64])) (const_int 8 [0x8]))) (set (reg:DI 133 [ _29 ]) (plus:DI (and:DI (ashift:DI (reg:DI 157) (const_int 4 [0x4])) (const_int 68719476720 [0xffffffff0])) (const_int 8 [0x8]))) (set (reg/f:DI 131 [ _27 ]) (mem/f/c:DI (unspec:DI [ (symbol_ref:DI ("*.LANCHOR0") [flags 0x182]) (reg:DI 2 2) ] UNSPEC_TOCREL) [91 node_sched_param_vec.m_vec+0 S8 A64])) ]) Trying 4 -> 29: 4: r139:DI=r159:DI REG_DEAD r159:DI 29: [r131:DI+r133:DI]=r139:DI#0 REG_DEAD r133:DI REG_DEAD r131:DI Failed to match this instruction: (parallel [ (set (mem:SI (plus:DI (reg/f:DI 131 [ _27 ]) (reg:DI 133 [ _29 ])) [6 _24->time+0 S4 A32]) (subreg:SI (reg:DI 159) 0)) (set (reg/v:DI 139 [ cycle ]) (reg:DI 159)) ]) Failed to match this instruction: (parallel [ (set (mem:SI (plus:DI (reg/f:DI 131 [ _27 ]) (reg:DI 133 [ _29 ])) [6 _24->time+0 S4 A32]) (subreg:SI (reg:DI 159) 0)) (set (reg/v:DI 139 [ cycle ]) (reg:DI 159)) ]) Trying 3 -> 35: 3: r138:DI=r158:DI REG_DEAD r158:DI 35: r149:SI=r139:DI#0/r138:DI#0 Failed to match this instruction: (parallel [ (set (reg:SI 149) (div:SI (subreg/s/u:SI (reg/v:DI 139 [ cycle ]) 0) (subreg/s/u:SI (reg:DI 158) 0))) (set (reg/v:DI 138 [ ii ]) (reg:DI 158)) ]) Failed to match this instruction: (parallel [ (set (reg:SI 149) (div:SI (subreg/s/u:SI (reg/v:DI 139 [ cycle ]) 0) (subreg/s/u:SI (reg:DI 158) 0))) (set (reg/v:DI 138 [ ii ]) (reg:DI 158)) ]) Trying 35 -> 36: 35: r149:SI=r139:DI#0/r138:DI#0 36: r151:SI=r149:SI*r138:DI#0 REG_DEAD r149:SI Failed to match this instruction: (set (reg:SI 151) (mult:SI (div:SI (subreg/s/u:SI (reg/v:DI 139 [ cycle ]) 0) (subreg/s/u:SI (reg/v:DI 138 [ ii ]) 0)) (subreg:SI (reg/v:DI 138 [ ii ]) 0))) Trying 3, 35 -> 36: 3: r138:DI=r158:DI REG_DEAD r158:DI 35: r149:SI=r139:DI#0/r138:DI#0 36: r151:SI=r149:SI*r138:DI#0 REG_DEAD r149:SI Failed to match this instruction: (parallel [ (set (reg:SI 151) (mult:SI (div:SI (subreg/s/u:SI (reg/v:DI 139 [ cycle ]) 0) (subreg/s/u:SI (reg:DI 158) 0)) (subreg:SI (reg:DI 158) 0))) (set (reg/v:DI 138 [ ii ]) (reg:DI 158)) ]) Failed to match this instruction: (parallel [ (set (reg:SI 151) (mult:SI (div:SI (subreg/s/u:SI (reg/v:DI 139 [ cycle ]) 0) (subreg/s/u:SI (reg:DI 158) 0)) (subreg:SI (reg:DI 158) 0))) (set (reg/v:DI 138 [ ii ]) (reg:DI 158)) ]) Successfully matched this instruction: (set (reg/v:DI 138 [ ii ]) (reg:DI 158)) Failed to match this instruction: (set (reg:SI 151) (mult:SI (div:SI (subreg/s/u:SI (reg/v:DI 139 [ cycle ]) 0) (subreg/s/u:SI (reg:DI 158) 0)) (subreg:SI (reg:DI 158) 0))) Trying 36 -> 37: 36: r151:SI=r149:SI*r138:DI#0 REG_DEAD r149:SI 37: r118:SI=r139:DI#0-r151:SI REG_DEAD r151:SI Failed to match this instruction: (set (reg:SI 118 [ _2 ]) (minus:SI (subreg:SI (reg/v:DI 139 [ cycle ]) 0) (mult:SI (reg:SI 149) (subreg:SI (reg/v:DI 138 [ ii ]) 0)))) Trying 35, 36 -> 37: 35: r149:SI=r139:DI#0/r138:DI#0 36: r151:SI=r149:SI*r138:DI#0 REG_DEAD r149:SI 37: r118:SI=r139:DI#0-r151:SI REG_DEAD r151:SI Failed to match this instruction: (set (reg:SI 118 [ _2 ]) (minus:SI (subreg:SI (reg/v:DI 139 [ cycle ]) 0) (mult:SI (div:SI (subreg/s/u:SI (reg/v:DI 139 [ cycle ]) 0) (subreg/s/u:SI (reg/v:DI 138 [ ii ]) 0)) (subreg:SI (reg/v:DI 138 [ ii ]) 0)))) Successfully matched this instruction: (set (reg:SI 151) (div:SI (subreg/s/u:SI (reg/v:DI 139 [ cycle ]) 0) (subreg/s/u:SI (reg/v:DI 138 [ ii ]) 0))) Failed to match this instruction: (set (reg:SI 118 [ _2 ]) (minus:SI (subreg:SI (reg/v:DI 139 [ cycle ]) 0) (mult:SI (reg:SI 151) (subreg:SI (reg/v:DI 138 [ ii ]) 0)))) Trying 5 -> 38: 5: r140:DI=r160:DI REG_DEAD r160:DI 38: r126:SI=r138:DI#0-r140:DI#0 REG_DEAD r140:DI Successfully matched this instruction: (set (reg:SI 126 [ _13 ]) (minus:SI (subreg:SI (reg/v:DI 138 [ ii ]) 0) (subreg:SI (reg:DI 160) 0))) allowing combination of insns 5 and 38 original costs 4 + 4 = 8 replacement cost 4 deferring deletion of insn with uid = 5. modifying insn i3 38: r126:SI=r138:DI#0-r160:DI#0 REG_DEAD r160:DI deferring rescan insn with uid = 38. Trying 38 -> 39: 38: r126:SI=r138:DI#0-r160:DI#0 REG_DEAD r160:DI 39: r132:SI=r126:SI-0x1 REG_DEAD r126:SI Failed to match this instruction: (set (reg:SI 132 [ _28 ]) (plus:SI (not:SI (subreg:SI (reg:DI 160) 0)) (subreg:SI (reg/v:DI 138 [ ii ]) 0))) Trying 39 -> 41: 39: r132:SI=r126:SI-0x1 REG_DEAD r126:SI 41: r136:SI=r132:SI/r138:DI#0 REG_DEAD r132:SI Failed to match this instruction: (set (reg:SI 136 [ _32 ]) (div:SI (plus:SI (reg:SI 126 [ _13 ]) (const_int -1 [0xffffffffffffffff])) (subreg/s/u:SI (reg/v:DI 138 [ ii ]) 0))) Trying 38, 39 -> 41: 38: r126:SI=r138:DI#0-r160:DI#0 REG_DEAD r160:DI 39: r132:SI=r126:SI-0x1 REG_DEAD r126:SI 41: r136:SI=r132:SI/r138:DI#0 REG_DEAD r132:SI Failed to match this instruction: (set (reg:SI 136 [ _32 ]) (div:SI (plus:SI (not:SI (subreg:SI (reg:DI 160) 0)) (subreg:SI (reg/v:DI 138 [ ii ]) 0)) (subreg/s/u:SI (reg/v:DI 138 [ ii ]) 0))) Successfully matched this instruction: (set (reg:SI 132 [ _28 ]) (not:SI (subreg:SI (reg:DI 160) 0))) Failed to match this instruction: (set (reg:SI 136 [ _32 ]) (div:SI (plus:SI (reg:SI 132 [ _28 ]) (subreg:SI (reg/v:DI 138 [ ii ]) 0)) (subreg/s/u:SI (reg/v:DI 138 [ ii ]) 0))) Trying 37 -> 44: 37: r118:SI=r139:DI#0-r151:SI REG_DEAD r151:SI 44: r153:CC=cmp(r118:SI,0) Failed to match this instruction: (parallel [ (set (reg:CC 153) (compare:CC (minus:SI (subreg/s/u:SI (reg/v:DI 139 [ cycle ]) 0) (reg:SI 151)) (const_int 0 [0]))) (set (reg:SI 118 [ _2 ]) (minus:SI (subreg/s/u:SI (reg/v:DI 139 [ cycle ]) 0) (reg:SI 151))) ]) Failed to match this instruction: (parallel [ (set (reg:CC 153) (compare:CC (minus:SI (subreg/s/u:SI (reg/v:DI 139 [ cycle ]) 0) (reg:SI 151)) (const_int 0 [0]))) (set (reg:SI 118 [ _2 ]) (minus:SI (subreg/s/u:SI (reg/v:DI 139 [ cycle ]) 0) (reg:SI 151))) ]) Successfully matched this instruction: (set (reg:SI 118 [ _2 ]) (minus:SI (subreg/s/u:SI (reg/v:DI 139 [ cycle ]) 0) (reg:SI 151))) Failed to match this instruction: (set (reg:CC 153) (compare:CC (minus:SI (subreg/s/u:SI (reg/v:DI 139 [ cycle ]) 0) (reg:SI 151)) (const_int 0 [0]))) Trying 36, 37 -> 44: 36: r151:SI=r149:SI*r138:DI#0 REG_DEAD r149:SI 37: r118:SI=r139:DI#0-r151:SI REG_DEAD r151:SI 44: r153:CC=cmp(r118:SI,0) Failed to match this instruction: (parallel [ (set (reg:CC 153) (compare:CC (minus:SI (subreg:SI (reg/v:DI 139 [ cycle ]) 0) (mult:SI (reg:SI 149) (subreg:SI (reg/v:DI 138 [ ii ]) 0))) (const_int 0 [0]))) (set (reg:SI 118 [ _2 ]) (minus:SI (subreg:SI (reg/v:DI 139 [ cycle ]) 0) (mult:SI (reg:SI 149) (subreg:SI (reg/v:DI 138 [ ii ]) 0)))) ]) Failed to match this instruction: (parallel [ (set (reg:CC 153) (compare:CC (minus:SI (subreg:SI (reg/v:DI 139 [ cycle ]) 0) (mult:SI (reg:SI 149) (subreg:SI (reg/v:DI 138 [ ii ]) 0))) (const_int 0 [0]))) (set (reg:SI 118 [ _2 ]) (minus:SI (subreg:SI (reg/v:DI 139 [ cycle ]) 0) (mult:SI (reg:SI 149) (subreg:SI (reg/v:DI 138 [ ii ]) 0)))) ]) Trying 44 -> 45: 44: r153:CC=cmp(r118:SI,0) 45: pc={(r153:CC>=0)?L56:pc} REG_DEAD r153:CC REG_BR_PROB 633507684 Failed to match this instruction: (set (pc) (if_then_else (ge (reg:SI 118 [ _2 ]) (const_int 0 [0])) (label_ref 56) (pc))) Trying 37, 44 -> 45: 37: r118:SI=r139:DI#0-r151:SI REG_DEAD r151:SI 44: r153:CC=cmp(r118:SI,0) 45: pc={(r153:CC>=0)?L56:pc} REG_DEAD r153:CC REG_BR_PROB 633507684 Failed to match this instruction: (parallel [ (set (pc) (if_then_else (ge (minus:SI (subreg:SI (reg/v:DI 139 [ cycle ]) 0) (reg:SI 151)) (const_int 0 [0])) (label_ref 56) (pc))) (set (reg:SI 118 [ _2 ]) (minus:SI (subreg/s/u:SI (reg/v:DI 139 [ cycle ]) 0) (reg:SI 151))) ]) Failed to match this instruction: (parallel [ (set (pc) (if_then_else (ge (minus:SI (subreg:SI (reg/v:DI 139 [ cycle ]) 0) (reg:SI 151)) (const_int 0 [0])) (label_ref 56) (pc))) (set (reg:SI 118 [ _2 ]) (minus:SI (subreg/s/u:SI (reg/v:DI 139 [ cycle ]) 0) (reg:SI 151))) ]) Successfully matched this instruction: (set (reg:SI 118 [ _2 ]) (minus:SI (subreg/s/u:SI (reg/v:DI 139 [ cycle ]) 0) (reg:SI 151))) Failed to match this instruction: (set (pc) (if_then_else (ge (minus:SI (subreg:SI (reg/v:DI 139 [ cycle ]) 0) (reg:SI 151)) (const_int 0 [0])) (label_ref 56) (pc))) Trying 47 -> 48: 47: r127:SI=r118:SI+r138:DI#0 REG_DEAD r118:SI 48: [r128:DI+0x4]=r127:SI REG_DEAD r127:SI Failed to match this instruction: (set (mem:SI (plus:DI (reg/f:DI 128 [ _24 ]) (const_int 4 [0x4])) [6 _24->row+0 S4 A32]) (plus:SI (reg:SI 118 [ _2 ]) (subreg:SI (reg/v:DI 138 [ ii ]) 0))) Trying 66 -> 67: 66: r154:CC=cmp(r139:DI#0,0) 67: pc={(r154:CC>=0)?L80:pc} REG_DEAD r154:CC REG_BR_PROB 914812532 Failed to match this instruction: (set (pc) (if_then_else (ge (subreg:SI (reg/v:DI 139 [ cycle ]) 0) (const_int 0 [0])) (label_ref 80) (pc))) Trying 71 -> 72: 71: r119:SI=r138:DI#0-r139:DI#0 REG_DEAD r139:DI 72: r120:SI=r119:SI-0x1 REG_DEAD r119:SI Failed to match this instruction: (set (reg:SI 120 [ _6 ]) (plus:SI (not:SI (subreg:SI (reg/v:DI 139 [ cycle ]) 0)) (subreg:SI (reg/v:DI 138 [ ii ]) 0))) Trying 72 -> 74: 72: r120:SI=r119:SI-0x1 REG_DEAD r119:SI 74: r134:SI=r120:SI/r138:DI#0 REG_DEAD r138:DI REG_DEAD r120:SI Failed to match this instruction: (set (reg/v:SI 134 [ stage ]) (div:SI (plus:SI (reg:SI 119 [ _5 ]) (const_int -1 [0xffffffffffffffff])) (subreg/s/u:SI (reg/v:DI 138 [ ii ]) 0))) Trying 71, 72 -> 74: 71: r119:SI=r138:DI#0-r139:DI#0 REG_DEAD r139:DI 72: r120:SI=r119:SI-0x1 REG_DEAD r119:SI 74: r134:SI=r120:SI/r138:DI#0 REG_DEAD r138:DI REG_DEAD r120:SI Failed to match this instruction: (set (reg/v:SI 134 [ stage ]) (div:SI (plus:SI (not:SI (subreg/s/u:SI (reg/v:DI 139 [ cycle ]) 0)) (subreg/s/u:SI (reg/v:DI 138 [ ii ]) 0)) (subreg/s/u:SI (reg/v:DI 138 [ ii ]) 0))) Successfully matched this instruction: (set (reg:SI 120 [ _6 ]) (not:SI (subreg/s/u:SI (reg/v:DI 139 [ cycle ]) 0))) Failed to match this instruction: (set (reg/v:SI 134 [ stage ]) (div:SI (plus:SI (reg:SI 120 [ _6 ]) (subreg/s/u:SI (reg/v:DI 138 [ ii ]) 0)) (subreg/s/u:SI (reg/v:DI 138 [ ii ]) 0))) Trying 74 -> 77: 74: r134:SI=r120:SI/r138:DI#0 REG_DEAD r138:DI REG_DEAD r120:SI 77: r125:SI=r136:SI-r134:SI REG_DEAD r136:SI REG_DEAD r134:SI Failed to match this instruction: (set (reg:SI 125 [ _12 ]) (minus:SI (reg:SI 136 [ _32 ]) (div:SI (reg:SI 120 [ _6 ]) (subreg/s/u:SI (reg/v:DI 138 [ ii ]) 0)))) Trying 72, 74 -> 77: 72: r120:SI=r119:SI-0x1 REG_DEAD r119:SI 74: r134:SI=r120:SI/r138:DI#0 REG_DEAD r138:DI REG_DEAD r120:SI 77: r125:SI=r136:SI-r134:SI REG_DEAD r136:SI REG_DEAD r134:SI Failed to match this instruction: (set (reg:SI 125 [ _12 ]) (minus:SI (reg:SI 136 [ _32 ]) (div:SI (plus:SI (reg:SI 119 [ _5 ]) (const_int -1 [0xffffffffffffffff])) (subreg/s/u:SI (reg/v:DI 138 [ ii ]) 0)))) Successfully matched this instruction: (set (reg/v:SI 134 [ stage ]) (plus:SI (reg:SI 119 [ _5 ]) (const_int -1 [0xffffffffffffffff]))) Failed to match this instruction: (set (reg:SI 125 [ _12 ]) (minus:SI (reg:SI 136 [ _32 ]) (div:SI (reg/v:SI 134 [ stage ]) (subreg/s/u:SI (reg/v:DI 138 [ ii ]) 0)))) Trying 83 -> 84: 83: r121:SI=r139:DI#0+0x1 REG_DEAD r139:DI 84: r122:SI=r121:SI+r138:DI#0 REG_DEAD r121:SI Failed to match this instruction: (set (reg:SI 122 [ _9 ]) (plus:SI (plus:SI (subreg:SI (reg/v:DI 139 [ cycle ]) 0) (subreg:SI (reg/v:DI 138 [ ii ]) 0)) (const_int 1 [0x1]))) Trying 84 -> 85: 84: r122:SI=r121:SI+r138:DI#0 REG_DEAD r121:SI 85: r123:SI=r122:SI-0x1 REG_DEAD r122:SI Failed to match this instruction: (set (reg:SI 123 [ _10 ]) (plus:SI (plus:SI (reg:SI 121 [ _8 ]) (subreg:SI (reg/v:DI 138 [ ii ]) 0)) (const_int -1 [0xffffffffffffffff]))) Trying 83, 84 -> 85: 83: r121:SI=r139:DI#0+0x1 REG_DEAD r139:DI 84: r122:SI=r121:SI+r138:DI#0 REG_DEAD r121:SI 85: r123:SI=r122:SI-0x1 REG_DEAD r122:SI Successfully matched this instruction: (set (reg:SI 123 [ _10 ]) (plus:SI (subreg:SI (reg/v:DI 139 [ cycle ]) 0) (subreg:SI (reg/v:DI 138 [ ii ]) 0))) allowing combination of insns 83, 84 and 85 original costs 4 + 4 + 4 = 12 replacement cost 4 deferring deletion of insn with uid = 84. deferring deletion of insn with uid = 83. modifying insn i3 85: r123:SI=r139:DI#0+r138:DI#0 REG_DEAD r139:DI deferring rescan insn with uid = 85. Trying 85 -> 87: 85: r123:SI=r139:DI#0+r138:DI#0 REG_DEAD r139:DI 87: r130:SI=r123:SI/r138:DI#0 REG_DEAD r138:DI REG_DEAD r123:SI Failed to match this instruction: (set (reg/v:SI 130 [ stage ]) (div:SI (plus:SI (subreg:SI (reg/v:DI 139 [ cycle ]) 0) (subreg:SI (reg/v:DI 138 [ ii ]) 0)) (subreg/s/u:SI (reg/v:DI 138 [ ii ]) 0))) Trying 87 -> 90: 87: r130:SI=r123:SI/r138:DI#0 REG_DEAD r138:DI REG_DEAD r123:SI 90: r124:SI=r130:SI+r136:SI REG_DEAD r136:SI REG_DEAD r130:SI Failed to match this instruction: (set (reg:SI 124 [ _11 ]) (plus:SI (div:SI (reg:SI 123 [ _10 ]) (subreg/s/u:SI (reg/v:DI 138 [ ii ]) 0)) (reg:SI 136 [ _32 ]))) Trying 85, 87 -> 90: 85: r123:SI=r139:DI#0+r138:DI#0 REG_DEAD r139:DI 87: r130:SI=r123:SI/r138:DI#0 REG_DEAD r138:DI REG_DEAD r123:SI 90: r124:SI=r130:SI+r136:SI REG_DEAD r136:SI REG_DEAD r130:SI Failed to match this instruction: (set (reg:SI 124 [ _11 ]) (plus:SI (div:SI (plus:SI (subreg:SI (reg/v:DI 139 [ cycle ]) 0) (subreg:SI (reg/v:DI 138 [ ii ]) 0)) (subreg/s/u:SI (reg/v:DI 138 [ ii ]) 0)) (reg:SI 136 [ _32 ]))) Successfully matched this instruction: (set (reg/v:SI 130 [ stage ]) (plus:SI (subreg:SI (reg/v:DI 139 [ cycle ]) 0) (subreg:SI (reg/v:DI 138 [ ii ]) 0))) Failed to match this instruction: (set (reg:SI 124 [ _11 ]) (plus:SI (div:SI (reg/v:SI 130 [ stage ]) (subreg/s/u:SI (reg/v:DI 138 [ ii ]) 0)) (reg:SI 136 [ _32 ]))) Trying 90 -> 91: 90: r124:SI=r130:SI+r136:SI REG_DEAD r136:SI REG_DEAD r130:SI 91: r125:SI=r124:SI-0x1 REG_DEAD r124:SI Failed to match this instruction: (set (reg:SI 125 [ _12 ]) (plus:SI (plus:SI (reg/v:SI 130 [ stage ]) (reg:SI 136 [ _32 ])) (const_int -1 [0xffffffffffffffff]))) Trying 87, 90 -> 91: 87: r130:SI=r123:SI/r138:DI#0 REG_DEAD r138:DI REG_DEAD r123:SI 90: r124:SI=r130:SI+r136:SI REG_DEAD r136:SI REG_DEAD r130:SI 91: r125:SI=r124:SI-0x1 REG_DEAD r124:SI Failed to match this instruction: (set (reg:SI 125 [ _12 ]) (plus:SI (plus:SI (div:SI (reg:SI 123 [ _10 ]) (subreg/s/u:SI (reg/v:DI 138 [ ii ]) 0)) (reg:SI 136 [ _32 ])) (const_int -1 [0xffffffffffffffff]))) Successfully matched this instruction: (set (reg:SI 124 [ _11 ]) (div:SI (reg:SI 123 [ _10 ]) (subreg/s/u:SI (reg/v:DI 138 [ ii ]) 0))) Failed to match this instruction: (set (reg:SI 125 [ _12 ]) (plus:SI (plus:SI (reg:SI 124 [ _11 ]) (reg:SI 136 [ _32 ])) (const_int -1 [0xffffffffffffffff]))) starting the processing of deferred insns rescanning insn with uid = 14. rescanning insn with uid = 19. rescanning insn with uid = 22. rescanning insn with uid = 38. rescanning insn with uid = 85. ending the processing of deferred insns update_node_sched_params Dataflow summary: ;; fully invalidated by EH 0 [0] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [0] 65 [1] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 78 [14] 79 [15] 80 [16] 81 [17] 82 [18] 83 [19] 96 [lr] 97 [ctr] 98 [ca] 100 [0] 101 [1] 105 [5] 106 [6] 107 [7] 109 [vscr] ;; hardware regs used 1 [1] 2 [2] 99 [ap] 109 [vscr] 110 [sfp] ;; regular block artificial uses 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] ;; eh block artificial uses 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] ;; entry block defs 1 [1] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 31 [31] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 96 [lr] 99 [ap] 109 [vscr] 110 [sfp] ;; exit block uses 1 [1] 2 [2] 31 [31] 108 [vrsave] 109 [vscr] 110 [sfp] ;; regs ever live 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] ;; ref usage r1={1d,7u} r2={1d,8u} r3={1d,1u} r4={1d,1u} r5={1d,1u} r6={1d,1u} r7={1d} r8={1d} r9={1d} r10={1d} r31={1d,7u} r33={1d} r34={1d} r35={1d} r36={1d} r37={1d} r38={1d} r39={1d} r40={1d} r41={1d} r42={1d} r43={1d} r44={1d} r45={1d} r66={1d} r67={1d} r68={1d} r69={1d} r70={1d} r71={1d} r72={1d} r73={1d} r74={1d} r75={1d} r76={1d} r77={1d} r96={1d} r99={1d,6u} r108={1u} r109={1d,1u} r110={1d,7u} r118={1d,3u} r119={1d,1u} r120={1d,1u} r123={1d,1u} r124={1d,1u} r125={2d,1u} r126={1d,1u} r127={1d,1u} r128={1d,3u} r130={1d,2u} r131={1d,3u} r132={1d,1u} r133={1d,2u} r134={1d,2u} r135={1d,1u} r136={1d,2u} r138={1d,11u} r139={1d,6u} r149={1d,1u} r151={1d,1u} r153={1d,1u} r154={1d,1u} r157={1d,3u} r158={1d,1u} r159={1d,1u} r160={1d,1u} ;; total ref usage 161{67d,94u,0e} in 63{63 regular + 0 call} insns. ;; basic block 2, loop depth 0, count 1073741824 (estimated locally), maybe hot ;; prev block 0, next block 3, flags: (RTL, MODIFIED) ;; pred: ENTRY [always] count:1073741824 (estimated locally) (FALLTHRU) ;; bb 2 artificial_defs: { } ;; bb 2 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] ;; lr use 1 [1] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 31 [31] 99 [ap] 110 [sfp] ;; lr def 118 126 128 129 131 132 133 135 136 137 138 139 140 149 151 153 157 158 159 160 ;; live in 1 [1] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] ;; live gen 118 126 128 129 131 132 133 135 136 137 138 139 140 149 151 153 157 158 159 160 ;; live kill (note 7 0 102 2 [bb 2] NOTE_INSN_BASIC_BLOCK) (insn 102 7 2 2 (set (reg:DI 157) (reg:DI 3 3 [ u ])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":470:1 687 {*movdi_internal64} (expr_list:REG_DEAD (reg:DI 3 3 [ u ]) (nil))) (note 2 102 103 2 NOTE_INSN_DELETED) (insn 103 2 3 2 (set (reg:DI 158) (reg:DI 4 4 [ ii ])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":470:1 687 {*movdi_internal64} (expr_list:REG_DEAD (reg:DI 4 4 [ ii ]) (nil))) (insn 3 103 104 2 (set (reg/v:DI 138 [ ii ]) (reg:DI 158)) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":470:1 687 {*movdi_internal64} (expr_list:REG_DEAD (reg:DI 158) (nil))) (insn 104 3 4 2 (set (reg:DI 159) (reg:DI 5 5 [ cycle ])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":470:1 687 {*movdi_internal64} (expr_list:REG_DEAD (reg:DI 5 5 [ cycle ]) (nil))) (insn 4 104 105 2 (set (reg/v:DI 139 [ cycle ]) (reg:DI 159)) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":470:1 687 {*movdi_internal64} (expr_list:REG_DEAD (reg:DI 159) (nil))) (insn 105 4 5 2 (set (reg:DI 160) (reg:DI 6 6 [ min_cycle ])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":470:1 687 {*movdi_internal64} (expr_list:REG_DEAD (reg:DI 6 6 [ min_cycle ]) (nil))) (note 5 105 6 2 NOTE_INSN_DELETED) (note 6 5 9 2 NOTE_INSN_FUNCTION_BEG) (debug_insn 9 6 10 2 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":471:3 -1 (nil)) (debug_insn 10 9 11 2 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":472:3 -1 (nil)) (debug_insn 11 10 13 2 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":474:3 -1 (nil)) (debug_insn 13 11 14 2 (var_location:DI this (symbol_ref:DI ("_ZL20node_sched_param_vec") [flags 0x82] )) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":474:3 -1 (nil)) (debug_insn 14 13 15 2 (var_location:SI ix (subreg:SI (reg:DI 157) 0)) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":474:3 -1 (nil)) (debug_insn 15 14 17 2 (debug_marker:BLK) "/builddir/gcc-13.2.1_git20231014/gcc/vec.h":1504:6 -1 (nil)) (insn 17 15 18 2 (set (reg/f:DI 131 [ _27 ]) (mem/f/c:DI (unspec:DI [ (symbol_ref:DI ("*.LANCHOR0") [flags 0x182]) (reg:DI 2 2) ] UNSPEC_TOCREL) [91 node_sched_param_vec.m_vec+0 S8 A64])) "/builddir/gcc-13.2.1_git20231014/gcc/vec.h":1505:14 687 {*movdi_internal64} (nil)) (debug_insn 18 17 19 2 (var_location:DI this (reg/f:DI 131 [ _27 ])) "/builddir/gcc-13.2.1_git20231014/gcc/vec.h":1505:14 -1 (nil)) (debug_insn 19 18 20 2 (var_location:SI ix (subreg:SI (reg:DI 157) 0)) "/builddir/gcc-13.2.1_git20231014/gcc/vec.h":1505:14 -1 (nil)) (debug_insn 20 19 21 2 (debug_marker:BLK) "/builddir/gcc-13.2.1_git20231014/gcc/vec.h":888:1 -1 (nil)) (note 21 20 22 2 NOTE_INSN_DELETED) (insn 22 21 23 2 (set (reg:DI 135 [ _31 ]) (and:DI (ashift:DI (reg:DI 157) (const_int 4 [0x4])) (const_int 68719476720 [0xffffffff0]))) "/builddir/gcc-13.2.1_git20231014/gcc/vec.h":891:20 discrim 1 247 {*rotldi3_mask} (expr_list:REG_DEAD (reg:DI 157) (nil))) (insn 23 22 24 2 (set (reg:DI 133 [ _29 ]) (plus:DI (reg:DI 135 [ _31 ]) (const_int 8 [0x8]))) 69 {*adddi3} (expr_list:REG_DEAD (reg:DI 135 [ _31 ]) (nil))) (insn 24 23 25 2 (set (reg/f:DI 128 [ _24 ]) (plus:DI (reg/f:DI 131 [ _27 ]) (reg:DI 133 [ _29 ]))) "/builddir/gcc-13.2.1_git20231014/gcc/vec.h":891:23 discrim 1 69 {*adddi3} (nil)) (debug_insn 25 24 26 2 (var_location:DI this (clobber (const_int 0 [0]))) "/builddir/gcc-13.2.1_git20231014/gcc/vec.h":1505:20 -1 (nil)) (debug_insn 26 25 27 2 (var_location:SI ix (clobber (const_int 0 [0]))) "/builddir/gcc-13.2.1_git20231014/gcc/vec.h":1505:20 -1 (nil)) (debug_insn 27 26 28 2 (var_location:DI this (clobber (const_int 0 [0]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":474:3 -1 (nil)) (debug_insn 28 27 29 2 (var_location:SI ix (clobber (const_int 0 [0]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":474:3 -1 (nil)) (insn 29 28 30 2 (set (mem:SI (plus:DI (reg/f:DI 131 [ _27 ]) (reg:DI 133 [ _29 ])) [6 _24->time+0 S4 A32]) (subreg/s/u:SI (reg/v:DI 139 [ cycle ]) 0)) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":474:18 discrim 1 560 {*movsi_internal1} (expr_list:REG_DEAD (reg:DI 133 [ _29 ]) (expr_list:REG_DEAD (reg/f:DI 131 [ _27 ]) (nil)))) (debug_insn 30 29 35 2 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":475:3 -1 (nil)) (insn 35 30 36 2 (set (reg:SI 149) (div:SI (subreg/s/u:SI (reg/v:DI 139 [ cycle ]) 0) (subreg/s/u:SI (reg/v:DI 138 [ ii ]) 0))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":475:19 184 {*divsi3} (nil)) (insn 36 35 37 2 (set (reg:SI 151) (mult:SI (reg:SI 149) (subreg/s/u:SI (reg/v:DI 138 [ ii ]) 0))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":475:19 159 {mulsi3} (expr_list:REG_DEAD (reg:SI 149) (nil))) (insn 37 36 38 2 (set (reg:SI 118 [ _2 ]) (minus:SI (subreg/s/u:SI (reg/v:DI 139 [ cycle ]) 0) (reg:SI 151))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":475:19 99 {*subfsi3} (expr_list:REG_DEAD (reg:SI 151) (nil))) (insn 38 37 39 2 (set (reg:SI 126 [ _13 ]) (minus:SI (subreg:SI (reg/v:DI 138 [ ii ]) 0) (subreg:SI (reg:DI 160) 0))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":479:25 99 {*subfsi3} (expr_list:REG_DEAD (reg:DI 160) (nil))) (insn 39 38 41 2 (set (reg:SI 132 [ _28 ]) (plus:SI (reg:SI 126 [ _13 ]) (const_int -1 [0xffffffffffffffff]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":479:25 68 {*addsi3} (expr_list:REG_DEAD (reg:SI 126 [ _13 ]) (nil))) (insn 41 39 44 2 (set (reg:SI 136 [ _32 ]) (div:SI (reg:SI 132 [ _28 ]) (subreg/s/u:SI (reg/v:DI 138 [ ii ]) 0))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":479:23 184 {*divsi3} (expr_list:REG_DEAD (reg:SI 132 [ _28 ]) (nil))) (insn 44 41 45 2 (set (reg:CC 153) (compare:CC (reg:SI 118 [ _2 ]) (const_int 0 [0]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":475:19 844 {*cmpsi_signed} (nil)) (jump_insn 45 44 46 2 (set (pc) (if_then_else (ge (reg:CC 153) (const_int 0 [0])) (label_ref 56) (pc))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":475:19 930 {*cbranch} (expr_list:REG_DEAD (reg:CC 153) (int_list:REG_BR_PROB 633507684 (nil))) -> 56) ;; succ: 3 [41.0% (guessed)] count:440234144 (estimated locally) (FALLTHRU) ;; 4 [59.0% (guessed)] count:633507680 (estimated locally) ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 128 136 138 139 ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 128 136 138 139 ;; basic block 3, loop depth 0, count 440234144 (estimated locally), maybe hot ;; prev block 2, next block 4, flags: (RTL) ;; pred: 2 [41.0% (guessed)] count:440234144 (estimated locally) (FALLTHRU) ;; bb 3 artificial_defs: { } ;; bb 3 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 128 136 138 139 ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 118 128 138 ;; lr def 127 ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 128 136 138 139 ;; live gen 127 ;; live kill (note 46 45 47 3 [bb 3] NOTE_INSN_BASIC_BLOCK) (insn 47 46 48 3 (set (reg:SI 127 [ iftmp.521_20 ]) (plus:SI (reg:SI 118 [ _2 ]) (subreg/s/u:SI (reg/v:DI 138 [ ii ]) 0))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":475:19 discrim 1 68 {*addsi3} (expr_list:REG_DEAD (reg:SI 118 [ _2 ]) (nil))) (insn 48 47 49 3 (set (mem:SI (plus:DI (reg/f:DI 128 [ _24 ]) (const_int 4 [0x4])) [6 _24->row+0 S4 A32]) (reg:SI 127 [ iftmp.521_20 ])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":475:17 discrim 1 560 {*movsi_internal1} (expr_list:REG_DEAD (reg:SI 127 [ iftmp.521_20 ]) (nil))) (debug_insn 49 48 50 3 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":479:3 -1 (nil)) (debug_insn 50 49 51 3 (var_location:SI D#58 (clobber (const_int 0 [0]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":479:25 -1 (nil)) (debug_insn 51 50 52 3 (var_location:SI D#57 (plus:SI (debug_expr:SI D#58) (const_int -1 [0xffffffffffffffff]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":479:25 -1 (nil)) (debug_insn 52 51 53 3 (var_location:SI sc_until_cycle_zero (div:SI (debug_expr:SI D#57) (subreg:SI (reg/v:DI 138 [ ii ]) 0))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":479:23 -1 (nil)) (debug_insn 53 52 56 3 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":481:3 -1 (nil)) ;; succ: 5 [always] count:440234144 (estimated locally) (FALLTHRU) ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 128 136 138 139 ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 128 136 138 139 ;; basic block 4, loop depth 0, count 633507680 (estimated locally), maybe hot ;; prev block 3, next block 5, flags: (RTL) ;; pred: 2 [59.0% (guessed)] count:633507680 (estimated locally) ;; bb 4 artificial_defs: { } ;; bb 4 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 128 136 138 139 ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 118 128 139 ;; lr def 154 ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 128 136 138 139 ;; live gen 154 ;; live kill (code_label 56 53 57 4 4 (nil) [1 uses]) (note 57 56 58 4 [bb 4] NOTE_INSN_BASIC_BLOCK) (insn 58 57 59 4 (set (mem:SI (plus:DI (reg/f:DI 128 [ _24 ]) (const_int 4 [0x4])) [6 _24->row+0 S4 A32]) (reg:SI 118 [ _2 ])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":475:17 discrim 1 560 {*movsi_internal1} (expr_list:REG_DEAD (reg:SI 118 [ _2 ]) (nil))) (debug_insn 59 58 60 4 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":479:3 -1 (nil)) (debug_insn 60 59 61 4 (var_location:SI D#60 (clobber (const_int 0 [0]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":479:25 -1 (nil)) (debug_insn 61 60 62 4 (var_location:SI D#59 (plus:SI (debug_expr:SI D#60) (const_int -1 [0xffffffffffffffff]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":479:25 -1 (nil)) (debug_insn 62 61 63 4 (var_location:SI sc_until_cycle_zero (div:SI (debug_expr:SI D#59) (subreg:SI (reg/v:DI 138 [ ii ]) 0))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":479:23 -1 (nil)) (debug_insn 63 62 66 4 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":481:3 -1 (nil)) (insn 66 63 67 4 (set (reg:CC 154) (compare:CC (subreg/s/u:SI (reg/v:DI 139 [ cycle ]) 0) (const_int 0 [0]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":481:3 discrim 1 844 {*cmpsi_signed} (nil)) (jump_insn 67 66 68 4 (set (pc) (if_then_else (ge (reg:CC 154) (const_int 0 [0])) (label_ref 80) (pc))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":481:3 discrim 1 930 {*cbranch} (expr_list:REG_DEAD (reg:CC 154) (int_list:REG_BR_PROB 914812532 (nil))) -> 80) ;; succ: 5 [14.8% (guessed)] count:93768285 (estimated locally) (FALLTHRU) ;; 6 [85.2% (guessed)] count:539739395 (estimated locally) ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 128 136 138 139 ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 128 136 138 139 ;; basic block 5, loop depth 0, count 440234144 (estimated locally), maybe hot ;; Invalid sum of incoming counts 534002429 (estimated locally), should be 440234144 (estimated locally) ;; prev block 4, next block 6, flags: (RTL) ;; pred: 4 [14.8% (guessed)] count:93768285 (estimated locally) (FALLTHRU) ;; 3 [always] count:440234144 (estimated locally) (FALLTHRU) ;; bb 5 artificial_defs: { } ;; bb 5 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 128 136 138 139 ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 136 138 139 ;; lr def 119 120 125 134 ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 128 136 138 139 ;; live gen 119 120 125 134 ;; live kill (code_label 68 67 69 5 5 (nil) [0 uses]) (note 69 68 70 5 [bb 5] NOTE_INSN_BASIC_BLOCK) (debug_insn 70 69 71 5 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":483:7 -1 (nil)) (insn 71 70 72 5 (set (reg:SI 119 [ _5 ]) (minus:SI (subreg/s/u:SI (reg/v:DI 138 [ ii ]) 0) (subreg/s/u:SI (reg/v:DI 139 [ cycle ]) 0))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":483:15 discrim 1 99 {*subfsi3} (expr_list:REG_DEAD (reg/v:DI 139 [ cycle ]) (nil))) (insn 72 71 74 5 (set (reg:SI 120 [ _6 ]) (plus:SI (reg:SI 119 [ _5 ]) (const_int -1 [0xffffffffffffffff]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":483:15 discrim 1 68 {*addsi3} (expr_list:REG_DEAD (reg:SI 119 [ _5 ]) (nil))) (insn 74 72 75 5 (set (reg/v:SI 134 [ stage ]) (div:SI (reg:SI 120 [ _6 ]) (subreg/s/u:SI (reg/v:DI 138 [ ii ]) 0))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":483:13 discrim 1 184 {*divsi3} (expr_list:REG_DEAD (reg/v:DI 138 [ ii ]) (expr_list:REG_DEAD (reg:SI 120 [ _6 ]) (nil)))) (debug_insn 75 74 76 5 (var_location:SI stage (reg/v:SI 134 [ stage ])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":483:13 discrim 1 -1 (nil)) (debug_insn 76 75 77 5 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":484:7 -1 (nil)) (insn 77 76 80 5 (set (reg:SI 125 [ _12 ]) (minus:SI (reg:SI 136 [ _32 ]) (reg/v:SI 134 [ stage ]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":484:45 99 {*subfsi3} (expr_list:REG_DEAD (reg:SI 136 [ _32 ]) (expr_list:REG_DEAD (reg/v:SI 134 [ stage ]) (nil)))) ;; succ: 7 [always] count:440234144 (estimated locally) (FALLTHRU) ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 125 128 ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 125 128 ;; basic block 6, loop depth 0, count 633507681 (estimated locally), maybe hot ;; Invalid sum of incoming counts 539739395 (estimated locally), should be 633507681 (estimated locally) ;; prev block 5, next block 7, flags: (RTL, MODIFIED) ;; pred: 4 [85.2% (guessed)] count:539739395 (estimated locally) ;; bb 6 artificial_defs: { } ;; bb 6 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 128 136 138 139 ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 136 138 139 ;; lr def 121 122 123 124 125 130 ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 128 136 138 139 ;; live gen 121 122 123 124 125 130 ;; live kill (code_label 80 77 81 6 6 (nil) [1 uses]) (note 81 80 82 6 [bb 6] NOTE_INSN_BASIC_BLOCK) (debug_insn 82 81 83 6 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":488:7 -1 (nil)) (note 83 82 84 6 NOTE_INSN_DELETED) (note 84 83 85 6 NOTE_INSN_DELETED) (insn 85 84 87 6 (set (reg:SI 123 [ _10 ]) (plus:SI (subreg:SI (reg/v:DI 139 [ cycle ]) 0) (subreg:SI (reg/v:DI 138 [ ii ]) 0))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":488:15 discrim 1 68 {*addsi3} (expr_list:REG_DEAD (reg/v:DI 139 [ cycle ]) (nil))) (insn 87 85 88 6 (set (reg/v:SI 130 [ stage ]) (div:SI (reg:SI 123 [ _10 ]) (subreg/s/u:SI (reg/v:DI 138 [ ii ]) 0))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":488:13 discrim 1 184 {*divsi3} (expr_list:REG_DEAD (reg/v:DI 138 [ ii ]) (expr_list:REG_DEAD (reg:SI 123 [ _10 ]) (nil)))) (debug_insn 88 87 89 6 (var_location:SI stage (reg/v:SI 130 [ stage ])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":488:13 discrim 1 -1 (nil)) (debug_insn 89 88 90 6 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":489:7 -1 (nil)) (insn 90 89 91 6 (set (reg:SI 124 [ _11 ]) (plus:SI (reg/v:SI 130 [ stage ]) (reg:SI 136 [ _32 ]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":489:45 68 {*addsi3} (expr_list:REG_DEAD (reg:SI 136 [ _32 ]) (expr_list:REG_DEAD (reg/v:SI 130 [ stage ]) (nil)))) (insn 91 90 92 6 (set (reg:SI 125 [ _12 ]) (plus:SI (reg:SI 124 [ _11 ]) (const_int -1 [0xffffffffffffffff]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":489:53 68 {*addsi3} (expr_list:REG_DEAD (reg:SI 124 [ _11 ]) (nil))) ;; succ: 7 [always] count:633507681 (estimated locally) (FALLTHRU) ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 125 128 ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 125 128 ;; basic block 7, loop depth 0, count 1073741824 (estimated locally), maybe hot ;; prev block 6, next block 1, flags: (RTL) ;; pred: 5 [always] count:440234144 (estimated locally) (FALLTHRU) ;; 6 [always] count:633507681 (estimated locally) (FALLTHRU) ;; bb 7 artificial_defs: { } ;; bb 7 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 125 128 ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 125 128 ;; lr def ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 125 128 ;; live gen ;; live kill (code_label 92 91 93 7 7 (nil) [0 uses]) (note 93 92 94 7 [bb 7] NOTE_INSN_BASIC_BLOCK) (insn 94 93 0 7 (set (mem:SI (plus:DI (reg/f:DI 128 [ _24 ]) (const_int 8 [0x8])) [6 _24->stage+0 S4 A32]) (reg:SI 125 [ _12 ])) 560 {*movsi_internal1} (expr_list:REG_DEAD (reg/f:DI 128 [ _24 ]) (expr_list:REG_DEAD (reg:SI 125 [ _12 ]) (nil)))) ;; succ: EXIT [always] count:1073741824 (estimated locally) (FALLTHRU) /builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc:491:1 ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] ;; Function rotate_partial_schedule (_ZL23rotate_partial_scheduleP16partial_schedulei, funcdef_no=2519, decl_uid=99235, cgraph_uid=1567, symbol_order=1618) scanning new insn with uid = 246. rescanning insn with uid = 2. scanning new insn with uid = 247. rescanning insn with uid = 3. starting the processing of deferred insns ending the processing of deferred insns df_analyze called df_worklist_dataflow_doublequeue: n_basic_blocks 17 n_edges 25 count 26 ( 1.5) rotate_partial_schedule Dataflow summary: def_info->table_size = 234, use_info->table_size = 0 ;; fully invalidated by EH 0 [0] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [0] 65 [1] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 78 [14] 79 [15] 80 [16] 81 [17] 82 [18] 83 [19] 96 [lr] 97 [ctr] 98 [ca] 100 [0] 101 [1] 105 [5] 106 [6] 107 [7] 109 [vscr] ;; hardware regs used 1 [1] 2 [2] 99 [ap] 109 [vscr] 110 [sfp] ;; regular block artificial uses 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] ;; eh block artificial uses 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] ;; entry block defs 1 [1] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 31 [31] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 96 [lr] 99 [ap] 109 [vscr] 110 [sfp] ;; exit block uses 1 [1] 2 [2] 31 [31] 108 [vrsave] 109 [vscr] 110 [sfp] ;; regs ever live 1 [1] 2 [2] 3 [3] 4 [4] 5 [5] 96 [lr] 98 [ca] 109 [vscr] ;; ref usage r0={2d} r1={1d,18u} r2={1d,18u} r3={5d,3u} r4={5d,3u} r5={5d,2u} r6={3d} r7={3d} r8={3d} r9={3d} r10={3d} r11={2d} r12={2d} r13={2d} r31={1d,16u} r32={2d} r33={3d} r34={3d} r35={3d} r36={3d} r37={3d} r38={3d} r39={3d} r40={3d} r41={3d} r42={3d} r43={3d} r44={3d} r45={3d} r64={2d} r65={2d} r66={3d} r67={3d} r68={3d} r69={3d} r70={3d} r71={3d} r72={3d} r73={3d} r74={3d} r75={3d} r76={3d} r77={3d} r78={2d} r79={2d} r80={2d} r81={2d} r82={2d} r83={2d} r96={3d} r97={2d} r98={6d,2u} r99={1d,15u} r100={2d} r101={2d} r105={2d} r106={2d} r107={2d} r108={1u} r109={3d,3u} r110={1d,16u} r117={1d,5u} r118={2d,5u} r119={1d,10u} r120={1d,10u} r121={3d,4u} r123={2d,4u} r124={3d,4u} r128={1d,2u} r129={1d,1u} r130={1d,1u} r131={1d,1u} r132={1d,1u} r133={1d,1u} r134={1d,1u} r135={1d,1u} r136={1d,1u} r137={1d,1u} r139={1d,2u} r141={1d,2u} r142={1d,2u} r143={2d,4u} r146={1d,2u} r147={1d,2u} r150={1d,2u} r151={1d,1u} r152={1d,1u} r153={1d,2u} r154={1d,1u} r156={1d,1u} r157={1d,1u} r158={1d,1u} r161={1d,8u} r162={1d,5u} r163={1d,1u} r173={1d,1u} r174={1d,1u} r177={1d,1u} r178={1d} r179={1d,1u} r180={1d,1u} r181={1d} r182={1d,1u} r183={1d,1u} r188={1d,1u} r189={2d,2u} r190={1d,3u} r191={1d,1u} r192={1d,1u} r193={1d,1u} r194={1d,1u} r195={1d,1u} r196={1d,1u} r197={1d,1u} r198={1d,1u} r199={1d,1u} r200={1d,3u} r201={1d,3u} r203={2d,2u} r207={1d,1u} r208={1d,1u} r210={1d,1u} r211={1d,1u} r212={1d,1u} r213={1d,1u} r214={1d,1u} ;; total ref usage 459{234d,225u,0e} in 143{141 regular + 2 call} insns. ( )->[0]->( 2 ) ;; bb 0 artificial_defs: { d2(1){ }d3(2){ }d8(3){ }d13(4){ }d18(5){ }d21(6){ }d24(7){ }d27(8){ }d30(9){ }d33(10){ }d40(31){ }d45(33){ }d48(34){ }d51(35){ }d54(36){ }d57(37){ }d60(38){ }d63(39){ }d66(40){ }d69(41){ }d72(42){ }d75(43){ }d78(44){ }d81(45){ }d88(66){ }d91(67){ }d94(68){ }d97(69){ }d100(70){ }d103(71){ }d106(72){ }d109(73){ }d112(74){ }d115(75){ }d118(76){ }d121(77){ }d136(96){ }d145(99){ }d158(109){ }d159(110){ }} ;; bb 0 artificial_uses: { } ;; lr in 108 [vrsave] ;; lr use ;; lr def 1 [1] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 31 [31] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 96 [lr] 99 [ap] 109 [vscr] 110 [sfp] ;; live in ;; live gen 1 [1] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 31 [31] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 96 [lr] 99 [ap] 109 [vscr] 110 [sfp] ;; live kill ;; lr out 1 [1] 2 [2] 3 [3] 4 [4] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] ;; live out 1 [1] 2 [2] 3 [3] 4 [4] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] ( 0 )->[2]->( 14 3 ) ;; bb 2 artificial_defs: { } ;; bb 2 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 3 [3] 4 [4] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] ;; lr use 1 [1] 2 [2] 3 [3] 4 [4] 31 [31] 99 [ap] 110 [sfp] ;; lr def 161 162 163 213 214 ;; live in 1 [1] 2 [2] 3 [3] 4 [4] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] ;; live gen 161 162 163 ;; live kill ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 161 162 ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 161 162 ( 2 )->[3]->( 4 5 ) ;; bb 3 artificial_defs: { } ;; bb 3 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 161 162 ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 161 162 ;; lr def 117 118 173 174 189 ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 161 162 ;; live gen 117 118 173 174 189 ;; live kill ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 117 118 161 162 189 ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 117 118 161 162 189 ( 3 )->[4]->( 5 ) ;; bb 4 artificial_defs: { } ;; bb 4 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 117 118 161 162 ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 117 118 ;; lr def 118 189 ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 117 118 161 162 ;; live gen 118 189 ;; live kill ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 117 118 161 162 189 ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 117 118 161 162 189 ( 4 3 )->[5]->( 6 13 ) ;; bb 5 artificial_defs: { } ;; bb 5 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 117 118 161 162 189 ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 189 ;; lr def ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 117 118 161 162 189 ;; live gen ;; live kill ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 117 118 161 162 ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 117 118 161 162 ( 5 )->[6]->( 7 ) ;; bb 6 artificial_defs: { } ;; bb 6 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 117 118 161 162 ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 117 161 ;; lr def 98 [ca] 119 120 128 129 130 131 132 137 139 143 146 147 150 151 152 153 154 158 177 178 179 180 181 182 183 190 191 192 193 194 195 ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 117 118 161 162 ;; live gen 98 [ca] 119 120 128 129 130 131 132 137 139 143 146 147 150 151 152 153 154 158 177 178 179 180 181 182 183 190 191 192 193 194 195 ;; live kill 98 [ca] ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 130 132 143 146 158 161 162 190 191 193 194 195 ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 119 120 130 132 143 146 158 161 162 190 191 193 194 195 ( 12 6 )->[7]->( 8 12 ) ;; bb 7 artificial_defs: { } ;; bb 7 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 130 132 143 146 158 161 162 190 191 193 194 195 ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 119 120 191 ;; lr def 141 142 ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 119 120 130 132 143 146 158 161 162 190 191 193 194 195 ;; live gen 141 142 ;; live kill ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 130 132 141 142 143 146 158 161 162 190 191 193 194 195 ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 119 120 130 132 141 142 143 146 158 161 162 190 191 193 194 195 ( 7 )->[8]->( 10 9 ) ;; bb 8 artificial_defs: { } ;; bb 8 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 130 132 141 142 143 146 158 161 162 190 191 193 194 195 ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 193 ;; lr def ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 119 120 130 132 141 142 143 146 158 161 162 190 191 193 194 195 ;; live gen ;; live kill ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 130 132 141 142 143 146 158 161 162 190 191 193 194 195 ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 119 120 130 132 141 142 143 146 158 161 162 190 191 193 194 195 ( 8 )->[9]->( 12 ) ;; bb 9 artificial_defs: { } ;; bb 9 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 130 132 141 142 143 146 158 161 162 190 191 193 194 195 ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 119 120 146 158 194 195 ;; lr def 0 [0] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [0] 65 [1] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 78 [14] 79 [15] 80 [16] 81 [17] 82 [18] 83 [19] 96 [lr] 97 [ctr] 98 [ca] 100 [0] 101 [1] 105 [5] 106 [6] 107 [7] 109 [vscr] ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 119 120 130 132 141 142 143 146 158 161 162 190 191 193 194 195 ;; live gen 3 [3] 4 [4] 5 [5] 109 [vscr] ;; live kill 96 [lr] ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 130 132 141 142 143 146 158 161 162 190 191 193 194 195 ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 119 120 130 132 141 142 143 146 158 161 162 190 191 193 194 195 ( 8 )->[10]->( 15 16 ) ;; bb 10 artificial_defs: { } ;; bb 10 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 130 132 141 142 143 146 158 161 162 190 191 193 194 195 ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 119 120 190 ;; lr def 121 123 124 196 197 198 199 ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 119 120 130 132 141 142 143 146 158 161 162 190 191 193 194 195 ;; live gen 121 123 124 196 197 198 199 ;; live kill ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 121 124 130 132 141 142 143 146 158 161 162 190 191 193 194 195 196 197 ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 119 120 121 123 124 130 132 141 142 143 146 158 161 162 190 191 193 194 195 196 197 ( 16 11 )->[11]->( 11 12 ) ;; bb 11 artificial_defs: { } ;; bb 11 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 121 124 130 132 141 142 143 146 158 161 162 190 191 193 194 195 203 ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 121 124 203 ;; lr def 121 124 156 157 200 201 203 207 208 ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 119 120 121 123 124 130 132 141 142 143 146 158 161 162 190 191 193 194 195 203 ;; live gen 121 123 124 156 157 200 201 202 203 207 208 ;; live kill ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 121 124 130 132 141 142 143 146 158 161 162 190 191 193 194 195 203 ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 119 120 121 123 124 130 132 141 142 143 146 158 161 162 190 191 193 194 195 203 ( 7 15 9 11 )->[12]->( 7 13 ) ;; bb 12 artificial_defs: { } ;; bb 12 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 130 132 141 142 143 146 158 161 162 190 191 193 194 195 ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 118 130 132 141 142 143 ;; lr def 143 188 ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 119 120 130 132 141 142 143 146 158 161 162 190 191 193 194 195 ;; live gen 143 188 ;; live kill ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 130 132 143 146 158 161 162 190 191 193 194 195 ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 119 120 130 132 143 146 158 161 162 190 191 193 194 195 ( 5 12 )->[13]->( 14 ) ;; bb 13 artificial_defs: { } ;; bb 13 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 161 162 ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 161 162 ;; lr def 133 134 135 136 ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 161 162 ;; live gen 133 134 135 136 ;; live kill ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] ( 13 2 )->[14]->( 1 ) ;; bb 14 artificial_defs: { } ;; bb 14 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] ;; lr def ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] ;; live gen ;; live kill ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] ( 10 )->[15]->( 16 12 ) ;; bb 15 artificial_defs: { } ;; bb 15 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 121 124 130 132 141 142 143 146 158 161 162 190 191 193 194 195 196 197 ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 119 120 121 124 196 ;; lr def 121 123 124 210 211 212 ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 119 120 121 124 130 132 141 142 143 146 158 161 162 190 191 193 194 195 196 197 ;; live gen 121 123 124 210 211 212 ;; live kill ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 121 124 130 132 141 142 143 146 158 161 162 190 191 193 194 195 197 ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 119 120 121 123 124 130 132 141 142 143 146 158 161 162 190 191 193 194 195 197 ( 15 10 )->[16]->( 11 ) ;; bb 16 artificial_defs: { } ;; bb 16 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 121 124 130 132 141 142 143 146 158 161 162 190 191 193 194 195 197 ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 197 ;; lr def 203 ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 119 120 121 123 124 130 132 141 142 143 146 158 161 162 190 191 193 194 195 197 ;; live gen 203 ;; live kill ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 121 124 130 132 141 142 143 146 158 161 162 190 191 193 194 195 203 ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 119 120 121 123 124 130 132 141 142 143 146 158 161 162 190 191 193 194 195 203 ( 14 )->[1]->( ) ;; bb 1 artificial_defs: { } ;; bb 1 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(108){ }u-1(109){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 108 [vrsave] 109 [vscr] 110 [sfp] ;; lr use 1 [1] 2 [2] 31 [31] 108 [vrsave] 109 [vscr] 110 [sfp] ;; lr def ;; live in 1 [1] 2 [2] 31 [31] 109 [vscr] 110 [sfp] ;; live gen ;; live kill ;; lr out ;; live out Finding needed instructions: Adding insn 14 to worklist Adding insn 29 to worklist Adding insn 41 to worklist Adding insn 85 to worklist Adding insn 89 to worklist Adding insn 100 to worklist Adding insn 95 to worklist Adding insn 212 to worklist Adding insn 238 to worklist Adding insn 223 to worklist Adding insn 219 to worklist Adding insn 124 to worklist Adding insn 118 to worklist Adding insn 147 to worklist Adding insn 140 to worklist Adding insn 138 to worklist Adding insn 157 to worklist Adding insn 153 to worklist Adding insn 204 to worklist Adding insn 198 to worklist Adding insn 194 to worklist Finished finding needed instructions: processing block 14 lr out = 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] processing block 13 lr out = 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] Adding insn 156 to worklist Adding insn 155 to worklist Adding insn 152 to worklist Adding insn 151 to worklist processing block 12 lr out = 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 130 132 143 146 158 161 162 190 191 193 194 195 Adding insn 146 to worklist Adding insn 142 to worklist processing block 11 lr out = 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 121 124 130 132 141 142 143 146 158 161 162 190 191 193 194 195 203 Adding insn 222 to worklist Adding insn 221 to worklist Adding insn 218 to worklist Adding insn 217 to worklist Adding insn 235 to worklist Adding insn 121 to worklist Adding insn 234 to worklist Adding insn 115 to worklist processing block 16 lr out = 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 121 124 130 132 141 142 143 146 158 161 162 190 191 193 194 195 203 Adding insn 239 to worklist processing block 15 lr out = 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 121 124 130 132 141 142 143 146 158 161 162 190 191 193 194 195 197 Adding insn 203 to worklist Adding insn 202 to worklist Adding insn 197 to worklist Adding insn 196 to worklist Adding insn 193 to worklist Adding insn 192 to worklist processing block 10 lr out = 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 121 124 130 132 141 142 143 146 158 161 162 190 191 193 194 195 196 197 Adding insn 211 to worklist Adding insn 186 to worklist Adding insn 185 to worklist Adding insn 184 to worklist Adding insn 109 to worklist Adding insn 107 to worklist Adding insn 106 to worklist processing block 9 lr out = 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 130 132 141 142 143 146 158 161 162 190 191 193 194 195 Adding insn 99 to worklist Adding insn 98 to worklist Adding insn 97 to worklist Adding insn 94 to worklist Adding insn 93 to worklist Adding insn 92 to worklist processing block 8 lr out = 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 130 132 141 142 143 146 158 161 162 190 191 193 194 195 processing block 7 lr out = 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 130 132 141 142 143 146 158 161 162 190 191 193 194 195 Adding insn 77 to worklist Adding insn 74 to worklist processing block 6 lr out = 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 130 132 143 146 158 161 162 190 191 193 194 195 Adding insn 96 to worklist Adding insn 91 to worklist Adding insn 88 to worklist Adding insn 87 to worklist Adding insn 169 to worklist Adding insn 5 to worklist Adding insn 70 to worklist Adding insn 69 to worklist Adding insn 68 to worklist Adding insn 66 to worklist Adding insn 65 to worklist Adding insn 64 to worklist Adding insn 63 to worklist Adding insn 62 to worklist Adding insn 61 to worklist Adding insn 59 to worklist Adding insn 58 to worklist Adding insn 57 to worklist Adding insn 56 to worklist Adding insn 55 to worklist Adding insn 54 to worklist Adding insn 53 to worklist Adding insn 52 to worklist Adding insn 50 to worklist Adding insn 49 to worklist Adding insn 48 to worklist Adding insn 47 to worklist Adding insn 46 to worklist Adding insn 45 to worklist Adding insn 44 to worklist Adding insn 43 to worklist processing block 5 lr out = 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 117 118 161 162 processing block 4 lr out = 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 117 118 161 162 189 Adding insn 168 to worklist Adding insn 31 to worklist processing block 3 lr out = 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 117 118 161 162 189 Adding insn 28 to worklist Adding insn 25 to worklist Adding insn 24 to worklist Adding insn 23 to worklist Adding insn 16 to worklist processing block 2 lr out = 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 161 162 Adding insn 13 to worklist Adding insn 3 to worklist Adding insn 247 to worklist Adding insn 2 to worklist Adding insn 246 to worklist df_worklist_dataflow_doublequeue: n_basic_blocks 17 n_edges 25 count 19 ( 1.1) insn_cost 4 for 246: r213:DI=%3:DI REG_DEAD %3:DI insn_cost 4 for 2: r161:DI=r213:DI REG_DEAD r213:DI insn_cost 4 for 247: r214:DI=%4:DI REG_DEAD %4:DI insn_cost 4 for 3: r162:DI=r214:DI REG_DEAD r214:DI insn_cost 0 for 8: debug begin stmt marker insn_cost 0 for 9: debug begin stmt marker insn_cost 0 for 10: debug D#61 => [r161:DI] insn_cost 0 for 11: debug last_row => D#61-0x1 insn_cost 0 for 12: debug begin stmt marker insn_cost 4 for 13: r163:CC=cmp(r162:DI,0) insn_cost 8 for 14: pc={(r163:CC==0)?L160:pc} REG_DEAD r163:CC REG_BR_PROB 365072228 insn_cost 8 for 16: r117:SI=[r161:DI] insn_cost 0 for 17: debug begin stmt marker insn_cost 76 for 23: r173:SI=r162:DI#0/r117:SI insn_cost 12 for 24: r174:SI=r173:SI*r117:SI REG_DEAD r173:SI insn_cost 4 for 25: r118:SI=r162:DI#0-r174:SI REG_DEAD r174:SI insn_cost 4 for 28: r189:CC=cmp(r118:SI,0) insn_cost 8 for 29: pc={(r189:CC>=0)?L32:pc} REG_BR_PROB 633507684 insn_cost 4 for 31: r118:SI=r118:SI+r117:SI insn_cost 4 for 168: r189:CC=cmp(r118:SI,0) insn_cost 0 for 34: debug backward_rotates => r118:SI insn_cost 0 for 35: debug begin stmt marker insn_cost 0 for 36: debug i => 0 insn_cost 0 for 37: debug begin stmt marker insn_cost 8 for 41: pc={(r189:CC<=0)?L148:pc} REG_DEAD r189:CC REG_BR_PROB 118111604 insn_cost 4 for 43: r190:SI=r117:SI-0x1 insn_cost 8 for 44: r119:DI=[r161:DI+0x8] insn_cost 8 for 45: r120:DI=[r161:DI+0x18] insn_cost 4 for 46: r128:DI=sign_extend(r190:SI) insn_cost 4 for 47: r129:DI=r128:DI<<0x3 insn_cost 4 for 48: r130:DI=r119:DI+r129:DI REG_DEAD r129:DI insn_cost 4 for 49: r131:DI=r128:DI<<0x2 REG_DEAD r128:DI insn_cost 4 for 50: r132:DI=r120:DI+r131:DI REG_DEAD r131:DI insn_cost 4 for 52: r154:SI=r117:SI-0x2 REG_DEAD r117:SI insn_cost 4 for 53: r153:DI=zero_extend(r154:SI) REG_DEAD r154:SI insn_cost 4 for 54: r152:DI=r153:DI+0x2 insn_cost 4 for 55: r151:DI=r152:DI<<0x3 REG_DEAD r152:DI insn_cost 4 for 56: r150:DI=r119:DI+r151:DI REG_DEAD r151:DI insn_cost 4 for 57: {r178:DI=r120:DI-r150:DI;ca:DI=leu(r150:DI,r120:DI);} REG_DEAD r150:DI REG_UNUSED r178:DI insn_cost 4 for 58: {r179:DI=ca:DI-0x1;clobber ca:DI;} REG_DEAD ca:DI REG_UNUSED ca:DI insn_cost 4 for 59: r177:DI=r179:DI+0x1 REG_DEAD r179:DI insn_cost 4 for 61: r147:DI=r153:DI+0x1 REG_DEAD r153:DI insn_cost 4 for 62: r146:DI=r147:DI<<0x2 insn_cost 4 for 63: r139:DI=r120:DI+r146:DI insn_cost 4 for 64: {r181:DI=r119:DI-r139:DI;ca:DI=leu(r139:DI,r119:DI);} REG_DEAD r139:DI REG_UNUSED r181:DI insn_cost 4 for 65: {r182:DI=ca:DI-0x1;clobber ca:DI;} REG_DEAD ca:DI REG_UNUSED ca:DI insn_cost 4 for 66: r180:DI=r182:DI+0x1 REG_DEAD r182:DI insn_cost 4 for 68: r183:SI=r180:DI#0|r177:DI#0 REG_DEAD r180:DI REG_DEAD r177:DI insn_cost 4 for 69: r137:QI=r183:SI#0 REG_DEAD r183:SI insn_cost 4 for 70: r158:DI=r147:DI<<0x3 REG_DEAD r147:DI insn_cost 4 for 5: r143:SI=0 insn_cost 4 for 169: r191:CC=cmp(r190:SI,0) insn_cost 4 for 87: r192:SI=zero_extend(r137:QI) REG_DEAD r137:QI insn_cost 4 for 88: r193:CC=cmp(r192:SI,0) REG_DEAD r192:SI insn_cost 4 for 91: r194:DI=r119:DI+0x8 insn_cost 4 for 96: r195:DI=r120:DI+0x4 insn_cost 0 for 72: debug i => r143:SI insn_cost 0 for 73: debug begin stmt marker insn_cost 8 for 74: r141:DI=[r119:DI] insn_cost 0 for 75: debug first_row => r141:DI insn_cost 0 for 76: debug begin stmt marker insn_cost 8 for 77: r142:SI=[r120:DI] insn_cost 0 for 78: debug first_row_length => r142:SI insn_cost 0 for 79: debug begin stmt marker insn_cost 0 for 80: debug row => 0 insn_cost 0 for 81: debug begin stmt marker insn_cost 8 for 85: pc={(r191:CC<=0)?L135:pc} REG_BR_PROB 118111604 insn_cost 8 for 89: pc={(r193:CC==0)?L103:pc} REG_BR_PROB 107374188 insn_cost 4 for 92: %5:DI=r158:DI insn_cost 4 for 93: %4:DI=r194:DI insn_cost 4 for 94: %3:DI=r119:DI insn_cost 8 for 95: %3:DI=call [`memmove'] argc:0 REG_DEAD %5:DI REG_DEAD %4:DI REG_UNUSED %3:DI REG_CALL_DECL `memmove' REG_EH_REGION 0 insn_cost 4 for 97: %5:DI=r146:DI insn_cost 4 for 98: %4:DI=r195:DI insn_cost 4 for 99: %3:DI=r120:DI insn_cost 8 for 100: %3:DI=call [`memmove'] argc:0 REG_DEAD %5:DI REG_DEAD %4:DI REG_UNUSED %3:DI REG_CALL_DECL `memmove' REG_EH_REGION 0 insn_cost 4 for 106: r123:DI=zero_extend(r190:SI) insn_cost 4 for 107: r121:DI=r119:DI-0x8 insn_cost 4 for 109: r124:DI=r120:DI-0x4 insn_cost 4 for 184: r196:DI=r123:DI-0x1 insn_cost 4 for 185: r197:DI=r123:DI insn_cost 4 for 186: r198:DI=r123:DI&0x1 REG_DEAD r123:DI insn_cost 4 for 211: r199:CC=cmp(r198:DI,0) REG_DEAD r198:DI insn_cost 8 for 212: pc={(r199:CC==0)?L210:pc} REG_DEAD r199:CC REG_BR_PROB 536870918 insn_cost 0 for 112: debug row => optimized away insn_cost 0 for 113: debug begin stmt marker insn_cost 8 for 115: r156:DI=[r121:DI+0x10] insn_cost 4 for 234: r200:DI=r121:DI+0x8 insn_cost 4 for 118: [r121:DI+0x8]=r156:DI REG_DEAD r156:DI REG_DEAD r121:DI insn_cost 0 for 119: debug begin stmt marker insn_cost 8 for 121: r157:SI=[r124:DI+0x8] insn_cost 4 for 235: r201:DI=r124:DI+0x4 insn_cost 4 for 124: [r124:DI+0x4]=r157:SI REG_DEAD r157:SI REG_DEAD r124:DI insn_cost 0 for 125: debug begin stmt marker insn_cost 0 for 126: debug row => optimized away insn_cost 0 for 127: debug begin stmt marker insn_cost 0 for 215: debug row => optimized away insn_cost 0 for 216: debug begin stmt marker insn_cost 8 for 217: r207:DI=[r200:DI+0x10] insn_cost 4 for 218: r121:DI=r200:DI+0x8 insn_cost 4 for 219: [r200:DI+0x8]=r207:DI REG_DEAD r207:DI REG_DEAD r200:DI insn_cost 0 for 220: debug begin stmt marker insn_cost 8 for 221: r208:SI=[r201:DI+0x8] insn_cost 4 for 222: r124:DI=r201:DI+0x4 insn_cost 4 for 223: [r201:DI+0x4]=r208:SI REG_DEAD r208:SI REG_DEAD r201:DI insn_cost 0 for 224: debug begin stmt marker insn_cost 0 for 225: debug row => optimized away insn_cost 0 for 226: debug begin stmt marker insn_cost 8 for 238: {pc={(r203:DI!=0x1)?L129:pc};r203:DI=r203:DI-0x1;clobber scratch;clobber scratch;} REG_BR_PROB 955630228 insn_cost 0 for 137: debug begin stmt marker insn_cost 4 for 138: [r130:DI]=r141:DI REG_DEAD r141:DI insn_cost 0 for 139: debug begin stmt marker insn_cost 4 for 140: [r132:DI]=r142:SI REG_DEAD r142:SI insn_cost 0 for 141: debug begin stmt marker insn_cost 4 for 142: r143:SI=r143:SI+0x1 insn_cost 0 for 143: debug i => r143:SI insn_cost 0 for 144: debug begin stmt marker insn_cost 4 for 146: r188:CC=cmp(r118:SI,r143:SI) insn_cost 8 for 147: pc={(r188:CC!=0)?L145:pc} REG_DEAD r188:CC REG_BR_PROB 955630228 insn_cost 0 for 150: debug begin stmt marker insn_cost 8 for 151: r133:SI=[r161:DI+0x24] insn_cost 4 for 152: r134:SI=r133:SI-r162:DI#0 REG_DEAD r133:SI insn_cost 4 for 153: [r161:DI+0x24]=r134:SI REG_DEAD r134:SI insn_cost 0 for 154: debug begin stmt marker insn_cost 8 for 155: r135:SI=[r161:DI+0x20] insn_cost 4 for 156: r136:SI=r135:SI-r162:DI#0 REG_DEAD r162:DI REG_DEAD r135:SI insn_cost 4 for 157: [r161:DI+0x20]=r136:SI REG_DEAD r161:DI REG_DEAD r136:SI insn_cost 0 for 190: debug row => optimized away insn_cost 0 for 191: debug begin stmt marker insn_cost 8 for 192: r210:DI=[r121:DI+0x10] REG_DEAD r121:DI insn_cost 4 for 193: r121:DI=r119:DI insn_cost 4 for 194: [r119:DI]=r210:DI REG_DEAD r210:DI insn_cost 0 for 195: debug begin stmt marker insn_cost 8 for 196: r211:SI=[r124:DI+0x8] REG_DEAD r124:DI insn_cost 4 for 197: r124:DI=r120:DI insn_cost 4 for 198: [r120:DI]=r211:SI REG_DEAD r211:SI insn_cost 0 for 199: debug begin stmt marker insn_cost 0 for 200: debug row => optimized away insn_cost 0 for 201: debug begin stmt marker insn_cost 4 for 202: r123:DI=r196:DI REG_DEAD r196:DI insn_cost 4 for 203: r212:CC=cmp(r123:DI,0) REG_DEAD r123:DI insn_cost 8 for 204: pc={(r212:CC!=0)?L210:pc} REG_DEAD r212:CC REG_BR_PROB 955630228 insn_cost 4 for 239: r203:DI=r197:DI 0>>0x1 REG_DEAD r197:DI Trying 3 -> 13: 3: r162:DI=r214:DI REG_DEAD r214:DI 13: r163:CC=cmp(r162:DI,0) Successfully matched this instruction: (parallel [ (set (reg:CC 163) (compare:CC (reg:DI 214) (const_int 0 [0]))) (set (reg/v:DI 162 [ start_cycle ]) (reg:DI 214)) ]) allowing combination of insns 3 and 13 original costs 4 + 4 = 8 replacement cost 4 deferring deletion of insn with uid = 3. modifying insn i3 13: {r163:CC=cmp(r214:DI,0);r162:DI=r214:DI;} REG_DEAD r214:DI deferring rescan insn with uid = 13. Trying 13 -> 14: 13: {r163:CC=cmp(r214:DI,0);r162:DI=r214:DI;} REG_DEAD r214:DI 14: pc={(r163:CC==0)?L160:pc} REG_DEAD r163:CC REG_BR_PROB 365072228 Failed to match this instruction: (parallel [ (set (pc) (if_then_else (eq (reg:DI 214) (const_int 0 [0])) (label_ref:DI 160) (pc))) (set (reg/v:DI 162 [ start_cycle ]) (reg:DI 214)) ]) Failed to match this instruction: (parallel [ (set (pc) (if_then_else (eq (reg:DI 214) (const_int 0 [0])) (label_ref:DI 160) (pc))) (set (reg/v:DI 162 [ start_cycle ]) (reg:DI 214)) ]) Successfully matched this instruction: (set (reg/v:DI 162 [ start_cycle ]) (reg:DI 214)) Failed to match this instruction: (set (pc) (if_then_else (eq (reg:DI 214) (const_int 0 [0])) (label_ref:DI 160) (pc))) Trying 16 -> 23: 16: r117:SI=[r161:DI] 23: r173:SI=r162:DI#0/r117:SI Failed to match this instruction: (parallel [ (set (reg:SI 173) (div:SI (subreg/s/u:SI (reg/v:DI 162 [ start_cycle ]) 0) (mem:SI (reg/v/f:DI 161 [ ps ]) [6 ps_33(D)->ii+0 S4 A64]))) (set (reg:SI 117 [ _1 ]) (mem:SI (reg/v/f:DI 161 [ ps ]) [6 ps_33(D)->ii+0 S4 A64])) ]) Failed to match this instruction: (parallel [ (set (reg:SI 173) (div:SI (subreg/s/u:SI (reg/v:DI 162 [ start_cycle ]) 0) (mem:SI (reg/v/f:DI 161 [ ps ]) [6 ps_33(D)->ii+0 S4 A64]))) (set (reg:SI 117 [ _1 ]) (mem:SI (reg/v/f:DI 161 [ ps ]) [6 ps_33(D)->ii+0 S4 A64])) ]) Trying 23 -> 24: 23: r173:SI=r162:DI#0/r117:SI 24: r174:SI=r173:SI*r117:SI REG_DEAD r173:SI Failed to match this instruction: (set (reg:SI 174) (mult:SI (div:SI (subreg/s/u:SI (reg/v:DI 162 [ start_cycle ]) 0) (reg:SI 117 [ _1 ])) (reg:SI 117 [ _1 ]))) Trying 16, 23 -> 24: 16: r117:SI=[r161:DI] 23: r173:SI=r162:DI#0/r117:SI 24: r174:SI=r173:SI*r117:SI REG_DEAD r173:SI Failed to match this instruction: (parallel [ (set (reg:SI 174) (mult:SI (div:SI (subreg/s/u:SI (reg/v:DI 162 [ start_cycle ]) 0) (mem:SI (reg/v/f:DI 161 [ ps ]) [6 ps_33(D)->ii+0 S4 A64])) (mem:SI (reg/v/f:DI 161 [ ps ]) [6 ps_33(D)->ii+0 S4 A64]))) (set (reg:SI 117 [ _1 ]) (mem:SI (reg/v/f:DI 161 [ ps ]) [6 ps_33(D)->ii+0 S4 A64])) ]) Failed to match this instruction: (parallel [ (set (reg:SI 174) (mult:SI (div:SI (subreg/s/u:SI (reg/v:DI 162 [ start_cycle ]) 0) (mem:SI (reg/v/f:DI 161 [ ps ]) [6 ps_33(D)->ii+0 S4 A64])) (mem:SI (reg/v/f:DI 161 [ ps ]) [6 ps_33(D)->ii+0 S4 A64]))) (set (reg:SI 117 [ _1 ]) (mem:SI (reg/v/f:DI 161 [ ps ]) [6 ps_33(D)->ii+0 S4 A64])) ]) Successfully matched this instruction: (set (reg:SI 117 [ _1 ]) (mem:SI (reg/v/f:DI 161 [ ps ]) [6 ps_33(D)->ii+0 S4 A64])) Failed to match this instruction: (set (reg:SI 174) (mult:SI (div:SI (subreg/s/u:SI (reg/v:DI 162 [ start_cycle ]) 0) (mem:SI (reg/v/f:DI 161 [ ps ]) [6 ps_33(D)->ii+0 S4 A64])) (mem:SI (reg/v/f:DI 161 [ ps ]) [6 ps_33(D)->ii+0 S4 A64]))) Trying 24 -> 25: 24: r174:SI=r173:SI*r117:SI REG_DEAD r173:SI 25: r118:SI=r162:DI#0-r174:SI REG_DEAD r174:SI Failed to match this instruction: (set (reg:SI 118 [ _2 ]) (minus:SI (subreg:SI (reg/v:DI 162 [ start_cycle ]) 0) (mult:SI (reg:SI 173) (reg:SI 117 [ _1 ])))) Trying 23, 24 -> 25: 23: r173:SI=r162:DI#0/r117:SI 24: r174:SI=r173:SI*r117:SI REG_DEAD r173:SI 25: r118:SI=r162:DI#0-r174:SI REG_DEAD r174:SI Failed to match this instruction: (set (reg:SI 118 [ _2 ]) (minus:SI (subreg:SI (reg/v:DI 162 [ start_cycle ]) 0) (mult:SI (div:SI (subreg/s/u:SI (reg/v:DI 162 [ start_cycle ]) 0) (reg:SI 117 [ _1 ])) (reg:SI 117 [ _1 ])))) Successfully matched this instruction: (set (reg:SI 174) (div:SI (subreg/s/u:SI (reg/v:DI 162 [ start_cycle ]) 0) (reg:SI 117 [ _1 ]))) Failed to match this instruction: (set (reg:SI 118 [ _2 ]) (minus:SI (subreg:SI (reg/v:DI 162 [ start_cycle ]) 0) (mult:SI (reg:SI 174) (reg:SI 117 [ _1 ])))) Trying 25 -> 28: 25: r118:SI=r162:DI#0-r174:SI REG_DEAD r174:SI 28: r189:CC=cmp(r118:SI,0) Failed to match this instruction: (parallel [ (set (reg:CC 189) (compare:CC (minus:SI (subreg/s/u:SI (reg/v:DI 162 [ start_cycle ]) 0) (reg:SI 174)) (const_int 0 [0]))) (set (reg:SI 118 [ _2 ]) (minus:SI (subreg/s/u:SI (reg/v:DI 162 [ start_cycle ]) 0) (reg:SI 174))) ]) Failed to match this instruction: (parallel [ (set (reg:CC 189) (compare:CC (minus:SI (subreg/s/u:SI (reg/v:DI 162 [ start_cycle ]) 0) (reg:SI 174)) (const_int 0 [0]))) (set (reg:SI 118 [ _2 ]) (minus:SI (subreg/s/u:SI (reg/v:DI 162 [ start_cycle ]) 0) (reg:SI 174))) ]) Successfully matched this instruction: (set (reg:SI 118 [ _2 ]) (minus:SI (subreg/s/u:SI (reg/v:DI 162 [ start_cycle ]) 0) (reg:SI 174))) Failed to match this instruction: (set (reg:CC 189) (compare:CC (minus:SI (subreg/s/u:SI (reg/v:DI 162 [ start_cycle ]) 0) (reg:SI 174)) (const_int 0 [0]))) Trying 24, 25 -> 28: 24: r174:SI=r173:SI*r117:SI REG_DEAD r173:SI 25: r118:SI=r162:DI#0-r174:SI REG_DEAD r174:SI 28: r189:CC=cmp(r118:SI,0) Failed to match this instruction: (parallel [ (set (reg:CC 189) (compare:CC (minus:SI (subreg/s/u:SI (reg/v:DI 162 [ start_cycle ]) 0) (mult:SI (reg:SI 173) (reg:SI 117 [ _1 ]))) (const_int 0 [0]))) (set (reg:SI 118 [ _2 ]) (minus:SI (subreg:SI (reg/v:DI 162 [ start_cycle ]) 0) (mult:SI (reg:SI 173) (reg:SI 117 [ _1 ])))) ]) Failed to match this instruction: (parallel [ (set (reg:CC 189) (compare:CC (minus:SI (subreg/s/u:SI (reg/v:DI 162 [ start_cycle ]) 0) (mult:SI (reg:SI 173) (reg:SI 117 [ _1 ]))) (const_int 0 [0]))) (set (reg:SI 118 [ _2 ]) (minus:SI (subreg:SI (reg/v:DI 162 [ start_cycle ]) 0) (mult:SI (reg:SI 173) (reg:SI 117 [ _1 ])))) ]) Trying 28 -> 29: 28: r189:CC=cmp(r118:SI,0) 29: pc={(r189:CC>=0)?L32:pc} REG_BR_PROB 633507684 Failed to match this instruction: (parallel [ (set (pc) (if_then_else (ge (reg:SI 118 [ _2 ]) (const_int 0 [0])) (label_ref 32) (pc))) (set (reg:CC 189) (compare:CC (reg:SI 118 [ _2 ]) (const_int 0 [0]))) ]) Failed to match this instruction: (parallel [ (set (pc) (if_then_else (ge (reg:SI 118 [ _2 ]) (const_int 0 [0])) (label_ref 32) (pc))) (set (reg:CC 189) (compare:CC (reg:SI 118 [ _2 ]) (const_int 0 [0]))) ]) Successfully matched this instruction: (set (reg:CC 189) (compare:CC (reg:SI 118 [ _2 ]) (const_int 0 [0]))) Failed to match this instruction: (set (pc) (if_then_else (ge (reg:SI 118 [ _2 ]) (const_int 0 [0])) (label_ref 32) (pc))) Trying 25, 28 -> 29: 25: r118:SI=r162:DI#0-r174:SI REG_DEAD r174:SI 28: r189:CC=cmp(r118:SI,0) 29: pc={(r189:CC>=0)?L32:pc} REG_BR_PROB 633507684 Failed to match this instruction: (parallel [ (set (pc) (if_then_else (ge (minus:SI (subreg:SI (reg/v:DI 162 [ start_cycle ]) 0) (reg:SI 174)) (const_int 0 [0])) (label_ref 32) (pc))) (set (reg:CC 189) (compare:CC (minus:SI (subreg/s/u:SI (reg/v:DI 162 [ start_cycle ]) 0) (reg:SI 174)) (const_int 0 [0]))) (set (reg:SI 118 [ _2 ]) (minus:SI (subreg/s/u:SI (reg/v:DI 162 [ start_cycle ]) 0) (reg:SI 174))) ]) Failed to match this instruction: (parallel [ (set (pc) (if_then_else (ge (minus:SI (subreg:SI (reg/v:DI 162 [ start_cycle ]) 0) (reg:SI 174)) (const_int 0 [0])) (label_ref 32) (pc))) (set (reg:CC 189) (compare:CC (minus:SI (subreg/s/u:SI (reg/v:DI 162 [ start_cycle ]) 0) (reg:SI 174)) (const_int 0 [0]))) (set (reg:SI 118 [ _2 ]) (minus:SI (subreg/s/u:SI (reg/v:DI 162 [ start_cycle ]) 0) (reg:SI 174))) ]) Trying 31 -> 168: 31: r118:SI=r118:SI+r117:SI 168: r189:CC=cmp(r118:SI,0) Failed to match this instruction: (parallel [ (set (reg:CC 189) (compare:CC (plus:SI (reg:SI 118 [ _2 ]) (reg:SI 117 [ _1 ])) (const_int 0 [0]))) (set (reg:SI 118 [ _2 ]) (plus:SI (reg:SI 118 [ _2 ]) (reg:SI 117 [ _1 ]))) ]) Failed to match this instruction: (parallel [ (set (reg:CC 189) (compare:CC (plus:SI (reg:SI 118 [ _2 ]) (reg:SI 117 [ _1 ])) (const_int 0 [0]))) (set (reg:SI 118 [ _2 ]) (plus:SI (reg:SI 118 [ _2 ]) (reg:SI 117 [ _1 ]))) ]) Trying 43 -> 46: 43: r190:SI=r117:SI-0x1 46: r128:DI=sign_extend(r190:SI) Failed to match this instruction: (parallel [ (set (reg:DI 128 [ _17 ]) (sign_extend:DI (plus:SI (reg:SI 117 [ _1 ]) (const_int -1 [0xffffffffffffffff])))) (set (reg:SI 190 [ _8 ]) (plus:SI (reg:SI 117 [ _1 ]) (const_int -1 [0xffffffffffffffff]))) ]) Failed to match this instruction: (parallel [ (set (reg:DI 128 [ _17 ]) (sign_extend:DI (plus:SI (reg:SI 117 [ _1 ]) (const_int -1 [0xffffffffffffffff])))) (set (reg:SI 190 [ _8 ]) (plus:SI (reg:SI 117 [ _1 ]) (const_int -1 [0xffffffffffffffff]))) ]) Successfully matched this instruction: (set (reg:SI 190 [ _8 ]) (plus:SI (reg:SI 117 [ _1 ]) (const_int -1 [0xffffffffffffffff]))) Failed to match this instruction: (set (reg:DI 128 [ _17 ]) (sign_extend:DI (plus:SI (reg:SI 117 [ _1 ]) (const_int -1 [0xffffffffffffffff])))) Trying 46 -> 47: 46: r128:DI=sign_extend(r190:SI) 47: r129:DI=r128:DI<<0x3 Failed to match this instruction: (parallel [ (set (reg:DI 129 [ _18 ]) (ashift:DI (sign_extend:DI (reg:SI 190 [ _8 ])) (const_int 3 [0x3]))) (set (reg:DI 128 [ _17 ]) (sign_extend:DI (reg:SI 190 [ _8 ]))) ]) Failed to match this instruction: (parallel [ (set (reg:DI 129 [ _18 ]) (ashift:DI (sign_extend:DI (reg:SI 190 [ _8 ])) (const_int 3 [0x3]))) (set (reg:DI 128 [ _17 ]) (sign_extend:DI (reg:SI 190 [ _8 ]))) ]) Successfully matched this instruction: (set (reg:DI 128 [ _17 ]) (sign_extend:DI (reg:SI 190 [ _8 ]))) Failed to match this instruction: (set (reg:DI 129 [ _18 ]) (ashift:DI (sign_extend:DI (reg:SI 190 [ _8 ])) (const_int 3 [0x3]))) Trying 43, 46 -> 47: 43: r190:SI=r117:SI-0x1 46: r128:DI=sign_extend(r190:SI) 47: r129:DI=r128:DI<<0x3 Failed to match this instruction: (parallel [ (set (reg:DI 129 [ _18 ]) (ashift:DI (sign_extend:DI (plus:SI (reg:SI 117 [ _1 ]) (const_int -1 [0xffffffffffffffff]))) (const_int 3 [0x3]))) (set (reg:DI 128 [ _17 ]) (sign_extend:DI (plus:SI (reg:SI 117 [ _1 ]) (const_int -1 [0xffffffffffffffff])))) (set (reg:SI 190 [ _8 ]) (plus:SI (reg:SI 117 [ _1 ]) (const_int -1 [0xffffffffffffffff]))) ]) Failed to match this instruction: (parallel [ (set (reg:DI 129 [ _18 ]) (ashift:DI (sign_extend:DI (plus:SI (reg:SI 117 [ _1 ]) (const_int -1 [0xffffffffffffffff]))) (const_int 3 [0x3]))) (set (reg:DI 128 [ _17 ]) (sign_extend:DI (plus:SI (reg:SI 117 [ _1 ]) (const_int -1 [0xffffffffffffffff])))) (set (reg:SI 190 [ _8 ]) (plus:SI (reg:SI 117 [ _1 ]) (const_int -1 [0xffffffffffffffff]))) ]) Trying 44 -> 48: 44: r119:DI=[r161:DI+0x8] 48: r130:DI=r119:DI+r129:DI REG_DEAD r129:DI Failed to match this instruction: (parallel [ (set (reg/f:DI 130 [ _19 ]) (plus:DI (mem/f:DI (plus:DI (reg/v/f:DI 161 [ ps ]) (const_int 8 [0x8])) [102 ps_33(D)->rows+0 S8 A64]) (reg:DI 129 [ _18 ]))) (set (reg/f:DI 119 [ _3 ]) (mem/f:DI (plus:DI (reg/v/f:DI 161 [ ps ]) (const_int 8 [0x8])) [102 ps_33(D)->rows+0 S8 A64])) ]) Failed to match this instruction: (parallel [ (set (reg/f:DI 130 [ _19 ]) (plus:DI (mem/f:DI (plus:DI (reg/v/f:DI 161 [ ps ]) (const_int 8 [0x8])) [102 ps_33(D)->rows+0 S8 A64]) (reg:DI 129 [ _18 ]))) (set (reg/f:DI 119 [ _3 ]) (mem/f:DI (plus:DI (reg/v/f:DI 161 [ ps ]) (const_int 8 [0x8])) [102 ps_33(D)->rows+0 S8 A64])) ]) Trying 47 -> 48: 47: r129:DI=r128:DI<<0x3 48: r130:DI=r119:DI+r129:DI REG_DEAD r129:DI Failed to match this instruction: (set (reg/f:DI 130 [ _19 ]) (plus:DI (ashift:DI (reg:DI 128 [ _17 ]) (const_int 3 [0x3])) (reg/f:DI 119 [ _3 ]))) Trying 46, 47 -> 48: 46: r128:DI=sign_extend(r190:SI) 47: r129:DI=r128:DI<<0x3 48: r130:DI=r119:DI+r129:DI REG_DEAD r129:DI Failed to match this instruction: (parallel [ (set (reg/f:DI 130 [ _19 ]) (plus:DI (ashift:DI (sign_extend:DI (reg:SI 190 [ _8 ])) (const_int 3 [0x3])) (reg/f:DI 119 [ _3 ]))) (set (reg:DI 128 [ _17 ]) (sign_extend:DI (reg:SI 190 [ _8 ]))) ]) Failed to match this instruction: (parallel [ (set (reg/f:DI 130 [ _19 ]) (plus:DI (ashift:DI (sign_extend:DI (reg:SI 190 [ _8 ])) (const_int 3 [0x3])) (reg/f:DI 119 [ _3 ]))) (set (reg:DI 128 [ _17 ]) (sign_extend:DI (reg:SI 190 [ _8 ]))) ]) Successfully matched this instruction: (set (reg:DI 128 [ _17 ]) (sign_extend:DI (reg:SI 190 [ _8 ]))) Failed to match this instruction: (set (reg/f:DI 130 [ _19 ]) (plus:DI (ashift:DI (sign_extend:DI (reg:SI 190 [ _8 ])) (const_int 3 [0x3])) (reg/f:DI 119 [ _3 ]))) Trying 47, 44 -> 48: 47: r129:DI=r128:DI<<0x3 44: r119:DI=[r161:DI+0x8] 48: r130:DI=r119:DI+r129:DI REG_DEAD r129:DI Failed to match this instruction: (parallel [ (set (reg/f:DI 130 [ _19 ]) (plus:DI (ashift:DI (reg:DI 128 [ _17 ]) (const_int 3 [0x3])) (mem/f:DI (plus:DI (reg/v/f:DI 161 [ ps ]) (const_int 8 [0x8])) [102 ps_33(D)->rows+0 S8 A64]))) (set (reg/f:DI 119 [ _3 ]) (mem/f:DI (plus:DI (reg/v/f:DI 161 [ ps ]) (const_int 8 [0x8])) [102 ps_33(D)->rows+0 S8 A64])) ]) Failed to match this instruction: (parallel [ (set (reg/f:DI 130 [ _19 ]) (plus:DI (ashift:DI (reg:DI 128 [ _17 ]) (const_int 3 [0x3])) (mem/f:DI (plus:DI (reg/v/f:DI 161 [ ps ]) (const_int 8 [0x8])) [102 ps_33(D)->rows+0 S8 A64]))) (set (reg/f:DI 119 [ _3 ]) (mem/f:DI (plus:DI (reg/v/f:DI 161 [ ps ]) (const_int 8 [0x8])) [102 ps_33(D)->rows+0 S8 A64])) ]) Successfully matched this instruction: (set (reg/f:DI 119 [ _3 ]) (mem/f:DI (plus:DI (reg/v/f:DI 161 [ ps ]) (const_int 8 [0x8])) [102 ps_33(D)->rows+0 S8 A64])) Failed to match this instruction: (set (reg/f:DI 130 [ _19 ]) (plus:DI (ashift:DI (reg:DI 128 [ _17 ]) (const_int 3 [0x3])) (mem/f:DI (plus:DI (reg/v/f:DI 161 [ ps ]) (const_int 8 [0x8])) [102 ps_33(D)->rows+0 S8 A64]))) Trying 43, 46, 47 -> 48: 43: r190:SI=r117:SI-0x1 46: r128:DI=sign_extend(r190:SI) 47: r129:DI=r128:DI<<0x3 48: r130:DI=r119:DI+r129:DI REG_DEAD r129:DI Failed to match this instruction: (parallel [ (set (reg/f:DI 130 [ _19 ]) (plus:DI (ashift:DI (sign_extend:DI (plus:SI (reg:SI 117 [ _1 ]) (const_int -1 [0xffffffffffffffff]))) (const_int 3 [0x3])) (reg/f:DI 119 [ _3 ]))) (set (reg:DI 128 [ _17 ]) (sign_extend:DI (plus:SI (reg:SI 117 [ _1 ]) (const_int -1 [0xffffffffffffffff])))) (set (reg:SI 190 [ _8 ]) (plus:SI (reg:SI 117 [ _1 ]) (const_int -1 [0xffffffffffffffff]))) ]) Failed to match this instruction: (parallel [ (set (reg/f:DI 130 [ _19 ]) (plus:DI (ashift:DI (sign_extend:DI (plus:SI (reg:SI 117 [ _1 ]) (const_int -1 [0xffffffffffffffff]))) (const_int 3 [0x3])) (reg/f:DI 119 [ _3 ]))) (set (reg:DI 128 [ _17 ]) (sign_extend:DI (plus:SI (reg:SI 117 [ _1 ]) (const_int -1 [0xffffffffffffffff])))) (set (reg:SI 190 [ _8 ]) (plus:SI (reg:SI 117 [ _1 ]) (const_int -1 [0xffffffffffffffff]))) ]) Trying 45 -> 50: 45: r120:DI=[r161:DI+0x18] 50: r132:DI=r120:DI+r131:DI REG_DEAD r131:DI Failed to match this instruction: (parallel [ (set (reg/f:DI 132 [ _21 ]) (plus:DI (mem/f:DI (plus:DI (reg/v/f:DI 161 [ ps ]) (const_int 24 [0x18])) [104 ps_33(D)->rows_length+0 S8 A64]) (reg:DI 131 [ _20 ]))) (set (reg/f:DI 120 [ _4 ]) (mem/f:DI (plus:DI (reg/v/f:DI 161 [ ps ]) (const_int 24 [0x18])) [104 ps_33(D)->rows_length+0 S8 A64])) ]) Failed to match this instruction: (parallel [ (set (reg/f:DI 132 [ _21 ]) (plus:DI (mem/f:DI (plus:DI (reg/v/f:DI 161 [ ps ]) (const_int 24 [0x18])) [104 ps_33(D)->rows_length+0 S8 A64]) (reg:DI 131 [ _20 ]))) (set (reg/f:DI 120 [ _4 ]) (mem/f:DI (plus:DI (reg/v/f:DI 161 [ ps ]) (const_int 24 [0x18])) [104 ps_33(D)->rows_length+0 S8 A64])) ]) Trying 49 -> 50: 49: r131:DI=r128:DI<<0x2 REG_DEAD r128:DI 50: r132:DI=r120:DI+r131:DI REG_DEAD r131:DI Failed to match this instruction: (set (reg/f:DI 132 [ _21 ]) (plus:DI (ashift:DI (reg:DI 128 [ _17 ]) (const_int 2 [0x2])) (reg/f:DI 120 [ _4 ]))) Trying 49, 45 -> 50: 49: r131:DI=r128:DI<<0x2 REG_DEAD r128:DI 45: r120:DI=[r161:DI+0x18] 50: r132:DI=r120:DI+r131:DI REG_DEAD r131:DI Failed to match this instruction: (parallel [ (set (reg/f:DI 132 [ _21 ]) (plus:DI (ashift:DI (reg:DI 128 [ _17 ]) (const_int 2 [0x2])) (mem/f:DI (plus:DI (reg/v/f:DI 161 [ ps ]) (const_int 24 [0x18])) [104 ps_33(D)->rows_length+0 S8 A64]))) (set (reg/f:DI 120 [ _4 ]) (mem/f:DI (plus:DI (reg/v/f:DI 161 [ ps ]) (const_int 24 [0x18])) [104 ps_33(D)->rows_length+0 S8 A64])) ]) Failed to match this instruction: (parallel [ (set (reg/f:DI 132 [ _21 ]) (plus:DI (ashift:DI (reg:DI 128 [ _17 ]) (const_int 2 [0x2])) (mem/f:DI (plus:DI (reg/v/f:DI 161 [ ps ]) (const_int 24 [0x18])) [104 ps_33(D)->rows_length+0 S8 A64]))) (set (reg/f:DI 120 [ _4 ]) (mem/f:DI (plus:DI (reg/v/f:DI 161 [ ps ]) (const_int 24 [0x18])) [104 ps_33(D)->rows_length+0 S8 A64])) ]) Successfully matched this instruction: (set (reg/f:DI 120 [ _4 ]) (mem/f:DI (plus:DI (reg/v/f:DI 161 [ ps ]) (const_int 24 [0x18])) [104 ps_33(D)->rows_length+0 S8 A64])) Failed to match this instruction: (set (reg/f:DI 132 [ _21 ]) (plus:DI (ashift:DI (reg:DI 128 [ _17 ]) (const_int 2 [0x2])) (mem/f:DI (plus:DI (reg/v/f:DI 161 [ ps ]) (const_int 24 [0x18])) [104 ps_33(D)->rows_length+0 S8 A64]))) Trying 52 -> 53: 52: r154:SI=r117:SI-0x2 REG_DEAD r117:SI 53: r153:DI=zero_extend(r154:SI) REG_DEAD r154:SI Failed to match this instruction: (set (reg:DI 153 [ _60 ]) (zero_extend:DI (plus:SI (reg:SI 117 [ _1 ]) (const_int -2 [0xfffffffffffffffe])))) Trying 53 -> 54: 53: r153:DI=zero_extend(r154:SI) REG_DEAD r154:SI 54: r152:DI=r153:DI+0x2 Failed to match this instruction: (parallel [ (set (reg:DI 152 [ _59 ]) (plus:DI (zero_extend:DI (reg:SI 154 [ _61 ])) (const_int 2 [0x2]))) (set (reg:DI 153 [ _60 ]) (zero_extend:DI (reg:SI 154 [ _61 ]))) ]) Failed to match this instruction: (parallel [ (set (reg:DI 152 [ _59 ]) (plus:DI (zero_extend:DI (reg:SI 154 [ _61 ])) (const_int 2 [0x2]))) (set (reg:DI 153 [ _60 ]) (zero_extend:DI (reg:SI 154 [ _61 ]))) ]) Successfully matched this instruction: (set (reg:DI 153 [ _60 ]) (zero_extend:DI (reg:SI 154 [ _61 ]))) Failed to match this instruction: (set (reg:DI 152 [ _59 ]) (plus:DI (zero_extend:DI (reg:SI 154 [ _61 ])) (const_int 2 [0x2]))) Trying 52, 53 -> 54: 52: r154:SI=r117:SI-0x2 REG_DEAD r117:SI 53: r153:DI=zero_extend(r154:SI) REG_DEAD r154:SI 54: r152:DI=r153:DI+0x2 Failed to match this instruction: (parallel [ (set (reg:DI 152 [ _59 ]) (plus:DI (zero_extend:DI (plus:SI (reg:SI 117 [ _1 ]) (const_int -2 [0xfffffffffffffffe]))) (const_int 2 [0x2]))) (set (reg:DI 153 [ _60 ]) (zero_extend:DI (plus:SI (reg:SI 117 [ _1 ]) (const_int -2 [0xfffffffffffffffe])))) ]) Failed to match this instruction: (parallel [ (set (reg:DI 152 [ _59 ]) (plus:DI (zero_extend:DI (plus:SI (reg:SI 117 [ _1 ]) (const_int -2 [0xfffffffffffffffe]))) (const_int 2 [0x2]))) (set (reg:DI 153 [ _60 ]) (zero_extend:DI (plus:SI (reg:SI 117 [ _1 ]) (const_int -2 [0xfffffffffffffffe])))) ]) Failed to match this instruction: (set (reg:DI 153 [ _60 ]) (zero_extend:DI (plus:SI (reg:SI 117 [ _1 ]) (const_int -2 [0xfffffffffffffffe])))) Trying 54 -> 55: 54: r152:DI=r153:DI+0x2 55: r151:DI=r152:DI<<0x3 REG_DEAD r152:DI Failed to match this instruction: (set (reg:DI 151 [ _58 ]) (plus:DI (ashift:DI (reg:DI 153 [ _60 ]) (const_int 3 [0x3])) (const_int 16 [0x10]))) Trying 53, 54 -> 55: 53: r153:DI=zero_extend(r154:SI) REG_DEAD r154:SI 54: r152:DI=r153:DI+0x2 55: r151:DI=r152:DI<<0x3 REG_DEAD r152:DI Failed to match this instruction: (parallel [ (set (reg:DI 151 [ _58 ]) (plus:DI (and:DI (ashift:DI (subreg:DI (reg:SI 154 [ _61 ]) 0) (const_int 3 [0x3])) (const_int 34359738360 [0x7fffffff8])) (const_int 16 [0x10]))) (set (reg:DI 153 [ _60 ]) (zero_extend:DI (reg:SI 154 [ _61 ]))) ]) Failed to match this instruction: (parallel [ (set (reg:DI 151 [ _58 ]) (plus:DI (and:DI (ashift:DI (subreg:DI (reg:SI 154 [ _61 ]) 0) (const_int 3 [0x3])) (const_int 34359738360 [0x7fffffff8])) (const_int 16 [0x10]))) (set (reg:DI 153 [ _60 ]) (zero_extend:DI (reg:SI 154 [ _61 ]))) ]) Successfully matched this instruction: (set (reg:DI 153 [ _60 ]) (zero_extend:DI (reg:SI 154 [ _61 ]))) Failed to match this instruction: (set (reg:DI 151 [ _58 ]) (plus:DI (and:DI (ashift:DI (subreg:DI (reg:SI 154 [ _61 ]) 0) (const_int 3 [0x3])) (const_int 34359738360 [0x7fffffff8])) (const_int 16 [0x10]))) Trying 52, 53, 54 -> 55: 52: r154:SI=r117:SI-0x2 REG_DEAD r117:SI 53: r153:DI=zero_extend(r154:SI) REG_DEAD r154:SI 54: r152:DI=r153:DI+0x2 55: r151:DI=r152:DI<<0x3 REG_DEAD r152:DI Failed to match this instruction: (parallel [ (set (reg:DI 151 [ _58 ]) (plus:DI (and:DI (ashift:DI (subreg:DI (plus:SI (reg:SI 117 [ _1 ]) (const_int -2 [0xfffffffffffffffe])) 0) (const_int 3 [0x3])) (const_int 34359738360 [0x7fffffff8])) (const_int 16 [0x10]))) (set (reg:DI 153 [ _60 ]) (zero_extend:DI (plus:SI (reg:SI 117 [ _1 ]) (const_int -2 [0xfffffffffffffffe])))) ]) Failed to match this instruction: (parallel [ (set (reg:DI 151 [ _58 ]) (plus:DI (and:DI (ashift:DI (subreg:DI (plus:SI (reg:SI 117 [ _1 ]) (const_int -2 [0xfffffffffffffffe])) 0) (const_int 3 [0x3])) (const_int 34359738360 [0x7fffffff8])) (const_int 16 [0x10]))) (set (reg:DI 153 [ _60 ]) (zero_extend:DI (plus:SI (reg:SI 117 [ _1 ]) (const_int -2 [0xfffffffffffffffe])))) ]) Failed to match this instruction: (set (reg:DI 153 [ _60 ]) (zero_extend:DI (plus:SI (reg:SI 117 [ _1 ]) (const_int -2 [0xfffffffffffffffe])))) Trying 55 -> 56: 55: r151:DI=r152:DI<<0x3 REG_DEAD r152:DI 56: r150:DI=r119:DI+r151:DI REG_DEAD r151:DI Failed to match this instruction: (set (reg/f:DI 150 [ _57 ]) (plus:DI (ashift:DI (reg:DI 152 [ _59 ]) (const_int 3 [0x3])) (reg/f:DI 119 [ _3 ]))) Trying 54, 55 -> 56: 54: r152:DI=r153:DI+0x2 55: r151:DI=r152:DI<<0x3 REG_DEAD r152:DI 56: r150:DI=r119:DI+r151:DI REG_DEAD r151:DI Failed to match this instruction: (set (reg/f:DI 150 [ _57 ]) (plus:DI (plus:DI (ashift:DI (reg:DI 153 [ _60 ]) (const_int 3 [0x3])) (reg/f:DI 119 [ _3 ])) (const_int 16 [0x10]))) Failed to match this instruction: (set (reg:DI 151 [ _58 ]) (plus:DI (ashift:DI (reg:DI 153 [ _60 ]) (const_int 3 [0x3])) (reg/f:DI 119 [ _3 ]))) Trying 53, 54, 55 -> 56: 53: r153:DI=zero_extend(r154:SI) REG_DEAD r154:SI 54: r152:DI=r153:DI+0x2 55: r151:DI=r152:DI<<0x3 REG_DEAD r152:DI 56: r150:DI=r119:DI+r151:DI REG_DEAD r151:DI Failed to match this instruction: (parallel [ (set (reg/f:DI 150 [ _57 ]) (plus:DI (plus:DI (and:DI (ashift:DI (subreg:DI (reg:SI 154 [ _61 ]) 0) (const_int 3 [0x3])) (const_int 34359738360 [0x7fffffff8])) (reg/f:DI 119 [ _3 ])) (const_int 16 [0x10]))) (set (reg:DI 153 [ _60 ]) (zero_extend:DI (reg:SI 154 [ _61 ]))) ]) Failed to match this instruction: (parallel [ (set (reg/f:DI 150 [ _57 ]) (plus:DI (plus:DI (and:DI (ashift:DI (subreg:DI (reg:SI 154 [ _61 ]) 0) (const_int 3 [0x3])) (const_int 34359738360 [0x7fffffff8])) (reg/f:DI 119 [ _3 ])) (const_int 16 [0x10]))) (set (reg:DI 153 [ _60 ]) (zero_extend:DI (reg:SI 154 [ _61 ]))) ]) Successfully matched this instruction: (set (reg:DI 153 [ _60 ]) (zero_extend:DI (reg:SI 154 [ _61 ]))) Failed to match this instruction: (set (reg/f:DI 150 [ _57 ]) (plus:DI (plus:DI (and:DI (ashift:DI (subreg:DI (reg:SI 154 [ _61 ]) 0) (const_int 3 [0x3])) (const_int 34359738360 [0x7fffffff8])) (reg/f:DI 119 [ _3 ])) (const_int 16 [0x10]))) Trying 56 -> 57: 56: r150:DI=r119:DI+r151:DI REG_DEAD r151:DI 57: {r178:DI=r120:DI-r150:DI;ca:DI=leu(r150:DI,r120:DI);} REG_DEAD r150:DI REG_UNUSED r178:DI Failed to match this instruction: (set (reg:DI 98 ca) (leu:DI (plus:DI (reg/f:DI 119 [ _3 ]) (reg:DI 151 [ _58 ])) (reg/f:DI 120 [ _4 ]))) Failed to match this instruction: (parallel [ (set (reg:DI 178) (minus:DI (minus:DI (reg/f:DI 120 [ _4 ]) (reg/f:DI 119 [ _3 ])) (reg:DI 151 [ _58 ]))) (set (reg:DI 98 ca) (leu:DI (plus:DI (reg/f:DI 119 [ _3 ]) (reg:DI 151 [ _58 ])) (reg/f:DI 120 [ _4 ]))) ]) Failed to match this instruction: (parallel [ (set (reg:DI 178) (minus:DI (minus:DI (reg/f:DI 120 [ _4 ]) (reg/f:DI 119 [ _3 ])) (reg:DI 151 [ _58 ]))) (set (reg:DI 98 ca) (leu:DI (plus:DI (reg/f:DI 119 [ _3 ]) (reg:DI 151 [ _58 ])) (reg/f:DI 120 [ _4 ]))) ]) Failed to match this instruction: (set (reg:DI 98 ca) (leu:DI (plus:DI (reg/f:DI 119 [ _3 ]) (reg:DI 151 [ _58 ])) (reg/f:DI 120 [ _4 ]))) Trying 55, 56 -> 57: 55: r151:DI=r152:DI<<0x3 REG_DEAD r152:DI 56: r150:DI=r119:DI+r151:DI REG_DEAD r151:DI 57: {r178:DI=r120:DI-r150:DI;ca:DI=leu(r150:DI,r120:DI);} REG_DEAD r150:DI REG_UNUSED r178:DI Failed to match this instruction: (set (reg:DI 98 ca) (leu:DI (plus:DI (ashift:DI (reg:DI 152 [ _59 ]) (const_int 3 [0x3])) (reg/f:DI 119 [ _3 ])) (reg/f:DI 120 [ _4 ]))) Failed to match this instruction: (parallel [ (set (reg:DI 178) (minus:DI (minus:DI (reg/f:DI 120 [ _4 ]) (reg/f:DI 119 [ _3 ])) (ashift:DI (reg:DI 152 [ _59 ]) (const_int 3 [0x3])))) (set (reg:DI 98 ca) (leu:DI (plus:DI (ashift:DI (reg:DI 152 [ _59 ]) (const_int 3 [0x3])) (reg/f:DI 119 [ _3 ])) (reg/f:DI 120 [ _4 ]))) ]) Failed to match this instruction: (parallel [ (set (reg:DI 178) (minus:DI (minus:DI (reg/f:DI 120 [ _4 ]) (reg/f:DI 119 [ _3 ])) (ashift:DI (reg:DI 152 [ _59 ]) (const_int 3 [0x3])))) (set (reg:DI 98 ca) (leu:DI (plus:DI (ashift:DI (reg:DI 152 [ _59 ]) (const_int 3 [0x3])) (reg/f:DI 119 [ _3 ])) (reg/f:DI 120 [ _4 ]))) ]) Failed to match this instruction: (set (reg:DI 98 ca) (leu:DI (plus:DI (ashift:DI (reg:DI 152 [ _59 ]) (const_int 3 [0x3])) (reg/f:DI 119 [ _3 ])) (reg/f:DI 120 [ _4 ]))) Trying 54, 55, 56 -> 57: 54: r152:DI=r153:DI+0x2 55: r151:DI=r152:DI<<0x3 REG_DEAD r152:DI 56: r150:DI=r119:DI+r151:DI REG_DEAD r151:DI 57: {r178:DI=r120:DI-r150:DI;ca:DI=leu(r150:DI,r120:DI);} REG_DEAD r150:DI REG_UNUSED r178:DI Failed to match this instruction: (set (reg:DI 98 ca) (leu:DI (plus:DI (plus:DI (ashift:DI (reg:DI 153 [ _60 ]) (const_int 3 [0x3])) (reg/f:DI 119 [ _3 ])) (const_int 16 [0x10])) (reg/f:DI 120 [ _4 ]))) Failed to match this instruction: (parallel [ (set (reg:DI 178) (plus:DI (minus:DI (minus:DI (reg/f:DI 120 [ _4 ]) (reg/f:DI 119 [ _3 ])) (ashift:DI (reg:DI 153 [ _60 ]) (const_int 3 [0x3]))) (const_int -16 [0xfffffffffffffff0]))) (set (reg:DI 98 ca) (leu:DI (plus:DI (plus:DI (ashift:DI (reg:DI 153 [ _60 ]) (const_int 3 [0x3])) (reg/f:DI 119 [ _3 ])) (const_int 16 [0x10])) (reg/f:DI 120 [ _4 ]))) ]) Failed to match this instruction: (parallel [ (set (reg:DI 178) (plus:DI (minus:DI (minus:DI (reg/f:DI 120 [ _4 ]) (reg/f:DI 119 [ _3 ])) (ashift:DI (reg:DI 153 [ _60 ]) (const_int 3 [0x3]))) (const_int -16 [0xfffffffffffffff0]))) (set (reg:DI 98 ca) (leu:DI (plus:DI (plus:DI (ashift:DI (reg:DI 153 [ _60 ]) (const_int 3 [0x3])) (reg/f:DI 119 [ _3 ])) (const_int 16 [0x10])) (reg/f:DI 120 [ _4 ]))) ]) Failed to match this instruction: (set (reg:DI 98 ca) (leu:DI (plus:DI (plus:DI (ashift:DI (reg:DI 153 [ _60 ]) (const_int 3 [0x3])) (reg/f:DI 119 [ _3 ])) (const_int 16 [0x10])) (reg/f:DI 120 [ _4 ]))) Trying 57 -> 58: 57: {r178:DI=r120:DI-r150:DI;ca:DI=leu(r150:DI,r120:DI);} REG_DEAD r150:DI REG_UNUSED r178:DI 58: {r179:DI=ca:DI-0x1;clobber ca:DI;} REG_DEAD ca:DI REG_UNUSED ca:DI Failed to match this instruction: (parallel [ (set (reg:DI 179) (neg:DI (gtu:DI (reg/f:DI 150 [ _57 ]) (reg/f:DI 120 [ _4 ])))) (clobber (reg:DI 98 ca)) (set (reg:DI 178) (minus:DI (reg/f:DI 120 [ _4 ]) (reg/f:DI 150 [ _57 ]))) ]) Failed to match this instruction: (parallel [ (set (reg:DI 179) (neg:DI (gtu:DI (reg/f:DI 150 [ _57 ]) (reg/f:DI 120 [ _4 ])))) (set (reg:DI 178) (minus:DI (reg/f:DI 120 [ _4 ]) (reg/f:DI 150 [ _57 ]))) ]) Successfully matched this instruction: (set (reg:DI 178) (minus:DI (reg/f:DI 120 [ _4 ]) (reg/f:DI 150 [ _57 ]))) Failed to match this instruction: (set (reg:DI 179) (neg:DI (gtu:DI (reg/f:DI 150 [ _57 ]) (reg/f:DI 120 [ _4 ])))) Trying 56, 57 -> 58: 56: r150:DI=r119:DI+r151:DI REG_DEAD r151:DI 57: {r178:DI=r120:DI-r150:DI;ca:DI=leu(r150:DI,r120:DI);} REG_DEAD r150:DI REG_UNUSED r178:DI 58: {r179:DI=ca:DI-0x1;clobber ca:DI;} REG_DEAD ca:DI REG_UNUSED ca:DI Failed to match this instruction: (parallel [ (set (reg:DI 179) (neg:DI (gtu:DI (plus:DI (reg/f:DI 119 [ _3 ]) (reg:DI 151 [ _58 ])) (reg/f:DI 120 [ _4 ])))) (clobber (reg:DI 98 ca)) (set (reg:DI 178) (minus:DI (minus:DI (reg/f:DI 120 [ _4 ]) (reg/f:DI 119 [ _3 ])) (reg:DI 151 [ _58 ]))) ]) Failed to match this instruction: (parallel [ (set (reg:DI 179) (neg:DI (gtu:DI (plus:DI (reg/f:DI 119 [ _3 ]) (reg:DI 151 [ _58 ])) (reg/f:DI 120 [ _4 ])))) (set (reg:DI 178) (minus:DI (minus:DI (reg/f:DI 120 [ _4 ]) (reg/f:DI 119 [ _3 ])) (reg:DI 151 [ _58 ]))) ]) Failed to match this instruction: (set (reg:DI 178) (minus:DI (minus:DI (reg/f:DI 120 [ _4 ]) (reg/f:DI 119 [ _3 ])) (reg:DI 151 [ _58 ]))) Trying 55, 56, 57 -> 58: 55: r151:DI=r152:DI<<0x3 REG_DEAD r152:DI 56: r150:DI=r119:DI+r151:DI REG_DEAD r151:DI 57: {r178:DI=r120:DI-r150:DI;ca:DI=leu(r150:DI,r120:DI);} REG_DEAD r150:DI REG_UNUSED r178:DI 58: {r179:DI=ca:DI-0x1;clobber ca:DI;} REG_DEAD ca:DI REG_UNUSED ca:DI Failed to match this instruction: (parallel [ (set (reg:DI 179) (neg:DI (gtu:DI (plus:DI (ashift:DI (reg:DI 152 [ _59 ]) (const_int 3 [0x3])) (reg/f:DI 119 [ _3 ])) (reg/f:DI 120 [ _4 ])))) (clobber (reg:DI 98 ca)) ]) Failed to match this instruction: (set (reg:DI 179) (neg:DI (gtu:DI (plus:DI (ashift:DI (reg:DI 152 [ _59 ]) (const_int 3 [0x3])) (reg/f:DI 119 [ _3 ])) (reg/f:DI 120 [ _4 ])))) Failed to match this instruction: (set (reg:DI 98 ca) (plus:DI (ashift:DI (reg:DI 152 [ _59 ]) (const_int 3 [0x3])) (reg/f:DI 119 [ _3 ]))) Trying 58 -> 59: 58: {r179:DI=ca:DI-0x1;clobber ca:DI;} REG_DEAD ca:DI REG_UNUSED ca:DI 59: r177:DI=r179:DI+0x1 REG_DEAD r179:DI Failed to match this instruction: (set (reg:DI 177) (reg:DI 98 ca)) Trying 57, 58 -> 59: 57: {r178:DI=r120:DI-r150:DI;ca:DI=leu(r150:DI,r120:DI);} REG_DEAD r150:DI REG_UNUSED r178:DI 58: {r179:DI=ca:DI-0x1;clobber ca:DI;} REG_DEAD ca:DI REG_UNUSED ca:DI 59: r177:DI=r179:DI+0x1 REG_DEAD r179:DI Failed to match this instruction: (set (reg:DI 177) (leu:DI (reg/f:DI 150 [ _57 ]) (reg/f:DI 120 [ _4 ]))) Trying 56, 57, 58 -> 59: 56: r150:DI=r119:DI+r151:DI REG_DEAD r151:DI 57: {r178:DI=r120:DI-r150:DI;ca:DI=leu(r150:DI,r120:DI);} REG_DEAD r150:DI REG_UNUSED r178:DI 58: {r179:DI=ca:DI-0x1;clobber ca:DI;} REG_DEAD ca:DI REG_UNUSED ca:DI 59: r177:DI=r179:DI+0x1 REG_DEAD r179:DI Failed to match this instruction: (set (reg:DI 177) (leu:DI (plus:DI (reg/f:DI 119 [ _3 ]) (reg:DI 151 [ _58 ])) (reg/f:DI 120 [ _4 ]))) Successfully matched this instruction: (set (reg:DI 179) (plus:DI (reg/f:DI 119 [ _3 ]) (reg:DI 151 [ _58 ]))) Failed to match this instruction: (set (reg:DI 177) (leu:DI (reg:DI 179) (reg/f:DI 120 [ _4 ]))) Trying 61 -> 62: 61: r147:DI=r153:DI+0x1 REG_DEAD r153:DI 62: r146:DI=r147:DI<<0x2 Failed to match this instruction: (parallel [ (set (reg:DI 146 [ _47 ]) (plus:DI (ashift:DI (reg:DI 153 [ _60 ]) (const_int 2 [0x2])) (const_int 4 [0x4]))) (set (reg:DI 147 [ _48 ]) (plus:DI (reg:DI 153 [ _60 ]) (const_int 1 [0x1]))) ]) Failed to match this instruction: (parallel [ (set (reg:DI 146 [ _47 ]) (plus:DI (ashift:DI (reg:DI 153 [ _60 ]) (const_int 2 [0x2])) (const_int 4 [0x4]))) (set (reg:DI 147 [ _48 ]) (plus:DI (reg:DI 153 [ _60 ]) (const_int 1 [0x1]))) ]) Successfully matched this instruction: (set (reg:DI 147 [ _48 ]) (plus:DI (reg:DI 153 [ _60 ]) (const_int 1 [0x1]))) Failed to match this instruction: (set (reg:DI 146 [ _47 ]) (plus:DI (ashift:DI (reg:DI 153 [ _60 ]) (const_int 2 [0x2])) (const_int 4 [0x4]))) Trying 62 -> 63: 62: r146:DI=r147:DI<<0x2 63: r139:DI=r120:DI+r146:DI Failed to match this instruction: (parallel [ (set (reg/f:DI 139 [ _30 ]) (plus:DI (ashift:DI (reg:DI 147 [ _48 ]) (const_int 2 [0x2])) (reg/f:DI 120 [ _4 ]))) (set (reg:DI 146 [ _47 ]) (ashift:DI (reg:DI 147 [ _48 ]) (const_int 2 [0x2]))) ]) Failed to match this instruction: (parallel [ (set (reg/f:DI 139 [ _30 ]) (plus:DI (ashift:DI (reg:DI 147 [ _48 ]) (const_int 2 [0x2])) (reg/f:DI 120 [ _4 ]))) (set (reg:DI 146 [ _47 ]) (ashift:DI (reg:DI 147 [ _48 ]) (const_int 2 [0x2]))) ]) Successfully matched this instruction: (set (reg:DI 146 [ _47 ]) (ashift:DI (reg:DI 147 [ _48 ]) (const_int 2 [0x2]))) Failed to match this instruction: (set (reg/f:DI 139 [ _30 ]) (plus:DI (ashift:DI (reg:DI 147 [ _48 ]) (const_int 2 [0x2])) (reg/f:DI 120 [ _4 ]))) Trying 61, 62 -> 63: 61: r147:DI=r153:DI+0x1 REG_DEAD r153:DI 62: r146:DI=r147:DI<<0x2 63: r139:DI=r120:DI+r146:DI Failed to match this instruction: (parallel [ (set (reg/f:DI 139 [ _30 ]) (plus:DI (plus:DI (ashift:DI (reg:DI 153 [ _60 ]) (const_int 2 [0x2])) (reg/f:DI 120 [ _4 ])) (const_int 4 [0x4]))) (set (reg:DI 146 [ _47 ]) (plus:DI (ashift:DI (reg:DI 153 [ _60 ]) (const_int 2 [0x2])) (const_int 4 [0x4]))) (set (reg:DI 147 [ _48 ]) (plus:DI (reg:DI 153 [ _60 ]) (const_int 1 [0x1]))) ]) Failed to match this instruction: (parallel [ (set (reg/f:DI 139 [ _30 ]) (plus:DI (plus:DI (ashift:DI (reg:DI 153 [ _60 ]) (const_int 2 [0x2])) (reg/f:DI 120 [ _4 ])) (const_int 4 [0x4]))) (set (reg:DI 146 [ _47 ]) (plus:DI (ashift:DI (reg:DI 153 [ _60 ]) (const_int 2 [0x2])) (const_int 4 [0x4]))) (set (reg:DI 147 [ _48 ]) (plus:DI (reg:DI 153 [ _60 ]) (const_int 1 [0x1]))) ]) Trying 63 -> 64: 63: r139:DI=r120:DI+r146:DI 64: {r181:DI=r119:DI-r139:DI;ca:DI=leu(r139:DI,r119:DI);} REG_DEAD r139:DI REG_UNUSED r181:DI Failed to match this instruction: (set (reg:DI 98 ca) (leu:DI (plus:DI (reg/f:DI 120 [ _4 ]) (reg:DI 146 [ _47 ])) (reg/f:DI 119 [ _3 ]))) Failed to match this instruction: (parallel [ (set (reg:DI 181) (minus:DI (minus:DI (reg/f:DI 119 [ _3 ]) (reg/f:DI 120 [ _4 ])) (reg:DI 146 [ _47 ]))) (set (reg:DI 98 ca) (leu:DI (plus:DI (reg/f:DI 120 [ _4 ]) (reg:DI 146 [ _47 ])) (reg/f:DI 119 [ _3 ]))) ]) Failed to match this instruction: (parallel [ (set (reg:DI 181) (minus:DI (minus:DI (reg/f:DI 119 [ _3 ]) (reg/f:DI 120 [ _4 ])) (reg:DI 146 [ _47 ]))) (set (reg:DI 98 ca) (leu:DI (plus:DI (reg/f:DI 120 [ _4 ]) (reg:DI 146 [ _47 ])) (reg/f:DI 119 [ _3 ]))) ]) Failed to match this instruction: (set (reg:DI 98 ca) (leu:DI (plus:DI (reg/f:DI 120 [ _4 ]) (reg:DI 146 [ _47 ])) (reg/f:DI 119 [ _3 ]))) Trying 62, 63 -> 64: 62: r146:DI=r147:DI<<0x2 63: r139:DI=r120:DI+r146:DI 64: {r181:DI=r119:DI-r139:DI;ca:DI=leu(r139:DI,r119:DI);} REG_DEAD r139:DI REG_UNUSED r181:DI Failed to match this instruction: (parallel [ (set (reg:DI 181) (minus:DI (minus:DI (reg/f:DI 119 [ _3 ]) (ashift:DI (reg:DI 147 [ _48 ]) (const_int 2 [0x2]))) (reg/f:DI 120 [ _4 ]))) (set (reg:DI 98 ca) (leu:DI (plus:DI (ashift:DI (reg:DI 147 [ _48 ]) (const_int 2 [0x2])) (reg/f:DI 120 [ _4 ])) (reg/f:DI 119 [ _3 ]))) (set (reg:DI 146 [ _47 ]) (ashift:DI (reg:DI 147 [ _48 ]) (const_int 2 [0x2]))) ]) Failed to match this instruction: (parallel [ (set (reg:DI 181) (minus:DI (minus:DI (reg/f:DI 119 [ _3 ]) (ashift:DI (reg:DI 147 [ _48 ]) (const_int 2 [0x2]))) (reg/f:DI 120 [ _4 ]))) (set (reg:DI 98 ca) (leu:DI (plus:DI (ashift:DI (reg:DI 147 [ _48 ]) (const_int 2 [0x2])) (reg/f:DI 120 [ _4 ])) (reg/f:DI 119 [ _3 ]))) (set (reg:DI 146 [ _47 ]) (ashift:DI (reg:DI 147 [ _48 ]) (const_int 2 [0x2]))) ]) Trying 61, 62, 63 -> 64: 61: r147:DI=r153:DI+0x1 REG_DEAD r153:DI 62: r146:DI=r147:DI<<0x2 63: r139:DI=r120:DI+r146:DI 64: {r181:DI=r119:DI-r139:DI;ca:DI=leu(r139:DI,r119:DI);} REG_DEAD r139:DI REG_UNUSED r181:DI Failed to match this instruction: (parallel [ (set (reg:DI 181) (plus:DI (minus:DI (minus:DI (reg/f:DI 119 [ _3 ]) (ashift:DI (reg:DI 153 [ _60 ]) (const_int 2 [0x2]))) (reg/f:DI 120 [ _4 ])) (const_int -4 [0xfffffffffffffffc]))) (set (reg:DI 98 ca) (leu:DI (plus:DI (plus:DI (ashift:DI (reg:DI 153 [ _60 ]) (const_int 2 [0x2])) (reg/f:DI 120 [ _4 ])) (const_int 4 [0x4])) (reg/f:DI 119 [ _3 ]))) (set (reg:DI 146 [ _47 ]) (plus:DI (ashift:DI (reg:DI 153 [ _60 ]) (const_int 2 [0x2])) (const_int 4 [0x4]))) (set (reg:DI 147 [ _48 ]) (plus:DI (reg:DI 153 [ _60 ]) (const_int 1 [0x1]))) ]) Failed to match this instruction: (parallel [ (set (reg:DI 181) (plus:DI (minus:DI (minus:DI (reg/f:DI 119 [ _3 ]) (ashift:DI (reg:DI 153 [ _60 ]) (const_int 2 [0x2]))) (reg/f:DI 120 [ _4 ])) (const_int -4 [0xfffffffffffffffc]))) (set (reg:DI 98 ca) (leu:DI (plus:DI (plus:DI (ashift:DI (reg:DI 153 [ _60 ]) (const_int 2 [0x2])) (reg/f:DI 120 [ _4 ])) (const_int 4 [0x4])) (reg/f:DI 119 [ _3 ]))) (set (reg:DI 146 [ _47 ]) (plus:DI (ashift:DI (reg:DI 153 [ _60 ]) (const_int 2 [0x2])) (const_int 4 [0x4]))) (set (reg:DI 147 [ _48 ]) (plus:DI (reg:DI 153 [ _60 ]) (const_int 1 [0x1]))) ]) Trying 64 -> 65: 64: {r181:DI=r119:DI-r139:DI;ca:DI=leu(r139:DI,r119:DI);} REG_DEAD r139:DI REG_UNUSED r181:DI 65: {r182:DI=ca:DI-0x1;clobber ca:DI;} REG_DEAD ca:DI REG_UNUSED ca:DI Failed to match this instruction: (parallel [ (set (reg:DI 182) (neg:DI (gtu:DI (reg/f:DI 139 [ _30 ]) (reg/f:DI 119 [ _3 ])))) (clobber (reg:DI 98 ca)) (set (reg:DI 181) (minus:DI (reg/f:DI 119 [ _3 ]) (reg/f:DI 139 [ _30 ]))) ]) Failed to match this instruction: (parallel [ (set (reg:DI 182) (neg:DI (gtu:DI (reg/f:DI 139 [ _30 ]) (reg/f:DI 119 [ _3 ])))) (set (reg:DI 181) (minus:DI (reg/f:DI 119 [ _3 ]) (reg/f:DI 139 [ _30 ]))) ]) Successfully matched this instruction: (set (reg:DI 181) (minus:DI (reg/f:DI 119 [ _3 ]) (reg/f:DI 139 [ _30 ]))) Failed to match this instruction: (set (reg:DI 182) (neg:DI (gtu:DI (reg/f:DI 139 [ _30 ]) (reg/f:DI 119 [ _3 ])))) Trying 63, 64 -> 65: 63: r139:DI=r120:DI+r146:DI 64: {r181:DI=r119:DI-r139:DI;ca:DI=leu(r139:DI,r119:DI);} REG_DEAD r139:DI REG_UNUSED r181:DI 65: {r182:DI=ca:DI-0x1;clobber ca:DI;} REG_DEAD ca:DI REG_UNUSED ca:DI Failed to match this instruction: (parallel [ (set (reg:DI 182) (neg:DI (gtu:DI (plus:DI (reg/f:DI 120 [ _4 ]) (reg:DI 146 [ _47 ])) (reg/f:DI 119 [ _3 ])))) (clobber (reg:DI 98 ca)) (set (reg:DI 181) (minus:DI (minus:DI (reg/f:DI 119 [ _3 ]) (reg/f:DI 120 [ _4 ])) (reg:DI 146 [ _47 ]))) ]) Failed to match this instruction: (parallel [ (set (reg:DI 182) (neg:DI (gtu:DI (plus:DI (reg/f:DI 120 [ _4 ]) (reg:DI 146 [ _47 ])) (reg/f:DI 119 [ _3 ])))) (set (reg:DI 181) (minus:DI (minus:DI (reg/f:DI 119 [ _3 ]) (reg/f:DI 120 [ _4 ])) (reg:DI 146 [ _47 ]))) ]) Failed to match this instruction: (set (reg:DI 181) (minus:DI (minus:DI (reg/f:DI 119 [ _3 ]) (reg/f:DI 120 [ _4 ])) (reg:DI 146 [ _47 ]))) Trying 62, 63, 64 -> 65: 62: r146:DI=r147:DI<<0x2 63: r139:DI=r120:DI+r146:DI 64: {r181:DI=r119:DI-r139:DI;ca:DI=leu(r139:DI,r119:DI);} REG_DEAD r139:DI REG_UNUSED r181:DI 65: {r182:DI=ca:DI-0x1;clobber ca:DI;} REG_DEAD ca:DI REG_UNUSED ca:DI Failed to match this instruction: (parallel [ (set (reg:DI 182) (neg:DI (gtu:DI (plus:DI (ashift:DI (reg:DI 147 [ _48 ]) (const_int 2 [0x2])) (reg/f:DI 120 [ _4 ])) (reg/f:DI 119 [ _3 ])))) (clobber (reg:DI 98 ca)) (set (reg:DI 146 [ _47 ]) (ashift:DI (reg:DI 147 [ _48 ]) (const_int 2 [0x2]))) ]) Failed to match this instruction: (parallel [ (set (reg:DI 182) (neg:DI (gtu:DI (plus:DI (ashift:DI (reg:DI 147 [ _48 ]) (const_int 2 [0x2])) (reg/f:DI 120 [ _4 ])) (reg/f:DI 119 [ _3 ])))) (set (reg:DI 146 [ _47 ]) (ashift:DI (reg:DI 147 [ _48 ]) (const_int 2 [0x2]))) ]) Successfully matched this instruction: (set (reg:DI 146 [ _47 ]) (ashift:DI (reg:DI 147 [ _48 ]) (const_int 2 [0x2]))) Failed to match this instruction: (set (reg:DI 182) (neg:DI (gtu:DI (plus:DI (ashift:DI (reg:DI 147 [ _48 ]) (const_int 2 [0x2])) (reg/f:DI 120 [ _4 ])) (reg/f:DI 119 [ _3 ])))) Trying 65 -> 66: 65: {r182:DI=ca:DI-0x1;clobber ca:DI;} REG_DEAD ca:DI REG_UNUSED ca:DI 66: r180:DI=r182:DI+0x1 REG_DEAD r182:DI Failed to match this instruction: (set (reg:DI 180) (reg:DI 98 ca)) Trying 64, 65 -> 66: 64: {r181:DI=r119:DI-r139:DI;ca:DI=leu(r139:DI,r119:DI);} REG_DEAD r139:DI REG_UNUSED r181:DI 65: {r182:DI=ca:DI-0x1;clobber ca:DI;} REG_DEAD ca:DI REG_UNUSED ca:DI 66: r180:DI=r182:DI+0x1 REG_DEAD r182:DI Failed to match this instruction: (set (reg:DI 180) (leu:DI (reg/f:DI 139 [ _30 ]) (reg/f:DI 119 [ _3 ]))) Trying 63, 64, 65 -> 66: 63: r139:DI=r120:DI+r146:DI 64: {r181:DI=r119:DI-r139:DI;ca:DI=leu(r139:DI,r119:DI);} REG_DEAD r139:DI REG_UNUSED r181:DI 65: {r182:DI=ca:DI-0x1;clobber ca:DI;} REG_DEAD ca:DI REG_UNUSED ca:DI 66: r180:DI=r182:DI+0x1 REG_DEAD r182:DI Failed to match this instruction: (set (reg:DI 180) (leu:DI (plus:DI (reg/f:DI 120 [ _4 ]) (reg:DI 146 [ _47 ])) (reg/f:DI 119 [ _3 ]))) Successfully matched this instruction: (set (reg:DI 182) (plus:DI (reg/f:DI 120 [ _4 ]) (reg:DI 146 [ _47 ]))) Failed to match this instruction: (set (reg:DI 180) (leu:DI (reg:DI 182) (reg/f:DI 119 [ _3 ]))) Trying 59 -> 68: 59: r177:DI=r179:DI+0x1 REG_DEAD r179:DI 68: r183:SI=r180:DI#0|r177:DI#0 REG_DEAD r180:DI REG_DEAD r177:DI Failed to match this instruction: (set (reg:SI 183) (ior:SI (plus:SI (subreg:SI (reg:DI 179) 0) (const_int 1 [0x1])) (subreg:SI (reg:DI 180) 0))) Trying 66 -> 68: 66: r180:DI=r182:DI+0x1 REG_DEAD r182:DI 68: r183:SI=r180:DI#0|r177:DI#0 REG_DEAD r180:DI REG_DEAD r177:DI Failed to match this instruction: (set (reg:SI 183) (ior:SI (plus:SI (subreg:SI (reg:DI 182) 0) (const_int 1 [0x1])) (subreg:SI (reg:DI 177) 0))) Trying 58, 59 -> 68: 58: {r179:DI=ca:DI-0x1;clobber ca:DI;} REG_DEAD ca:DI REG_UNUSED ca:DI 59: r177:DI=r179:DI+0x1 REG_DEAD r179:DI 68: r183:SI=r180:DI#0|r177:DI#0 REG_DEAD r180:DI REG_DEAD r177:DI Can't combine i1 into i3 Trying 65, 66 -> 68: 65: {r182:DI=ca:DI-0x1;clobber ca:DI;} REG_DEAD ca:DI REG_UNUSED ca:DI 66: r180:DI=r182:DI+0x1 REG_DEAD r182:DI 68: r183:SI=r180:DI#0|r177:DI#0 REG_DEAD r180:DI REG_DEAD r177:DI Failed to match this instruction: (set (reg:SI 183) (ior:SI (reg:SI 98 ca) (subreg:SI (reg:DI 177) 0))) EMERGENCY DUMP: rotate_partial_schedule Dataflow summary: ;; fully invalidated by EH 0 [0] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [0] 65 [1] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 78 [14] 79 [15] 80 [16] 81 [17] 82 [18] 83 [19] 96 [lr] 97 [ctr] 98 [ca] 100 [0] 101 [1] 105 [5] 106 [6] 107 [7] 109 [vscr] ;; hardware regs used 1 [1] 2 [2] 99 [ap] 109 [vscr] 110 [sfp] ;; regular block artificial uses 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] ;; eh block artificial uses 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] ;; entry block defs 1 [1] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 31 [31] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 96 [lr] 99 [ap] 109 [vscr] 110 [sfp] ;; exit block uses 1 [1] 2 [2] 31 [31] 108 [vrsave] 109 [vscr] 110 [sfp] ;; regs ever live 1 [1] 2 [2] 3 [3] 4 [4] 5 [5] 96 [lr] 98 [ca] 109 [vscr] ;; ref usage r0={2d} r1={1d,18u} r2={1d,18u} r3={5d,3u} r4={5d,3u} r5={5d,2u} r6={3d} r7={3d} r8={3d} r9={3d} r10={3d} r11={2d} r12={2d} r13={2d} r31={1d,16u} r32={2d} r33={3d} r34={3d} r35={3d} r36={3d} r37={3d} r38={3d} r39={3d} r40={3d} r41={3d} r42={3d} r43={3d} r44={3d} r45={3d} r64={2d} r65={2d} r66={3d} r67={3d} r68={3d} r69={3d} r70={3d} r71={3d} r72={3d} r73={3d} r74={3d} r75={3d} r76={3d} r77={3d} r78={2d} r79={2d} r80={2d} r81={2d} r82={2d} r83={2d} r96={3d} r97={2d} r98={6d,2u} r99={1d,15u} r100={2d} r101={2d} r105={2d} r106={2d} r107={2d} r108={1u} r109={3d,3u} r110={1d,16u} r117={1d,5u} r118={2d,5u} r119={1d,10u} r120={1d,10u} r121={3d,4u} r123={2d,4u} r124={3d,4u} r128={1d,2u} r129={1d,1u} r130={1d,1u} r131={1d,1u} r132={1d,1u} r133={1d,1u} r134={1d,1u} r135={1d,1u} r136={1d,1u} r137={1d,1u} r139={1d,2u} r141={1d,2u} r142={1d,2u} r143={2d,4u} r146={1d,2u} r147={1d,2u} r150={1d,2u} r151={1d,1u} r152={1d,1u} r153={1d,2u} r154={1d,1u} r156={1d,1u} r157={1d,1u} r158={1d,1u} r161={1d,8u} r162={1d,5u} r163={1d,1u} r173={1d,1u} r174={1d,1u} r177={1d,1u} r178={1d} r179={1d,1u} r180={1d,1u} r181={1d} r182={1d,1u} r183={1d,1u} r188={1d,1u} r189={2d,2u} r190={1d,3u} r191={1d,1u} r192={1d,1u} r193={1d,1u} r194={1d,1u} r195={1d,1u} r196={1d,1u} r197={1d,1u} r198={1d,1u} r199={1d,1u} r200={1d,3u} r201={1d,3u} r203={2d,2u} r207={1d,1u} r208={1d,1u} r210={1d,1u} r211={1d,1u} r212={1d,1u} r213={1d,1u} r214={1d,1u} ;; total ref usage 459{234d,225u,0e} in 142{140 regular + 2 call} insns. ;; basic block 2, loop depth 0, count 22118277 (estimated locally), maybe hot ;; prev block 0, next block 3, flags: (REACHABLE, RTL, MODIFIED) ;; pred: ENTRY [always] count:22118277 (estimated locally) (FALLTHRU) ;; bb 2 artificial_defs: { } ;; bb 2 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 3 [3] 4 [4] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] ;; lr use 1 [1] 2 [2] 3 [3] 4 [4] 31 [31] 99 [ap] 110 [sfp] ;; lr def 161 162 163 213 214 ;; live in 1 [1] 2 [2] 3 [3] 4 [4] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] ;; live gen 161 162 163 213 214 ;; live kill (note 6 0 246 2 [bb 2] NOTE_INSN_BASIC_BLOCK) (insn 246 6 2 2 (set (reg:DI 213) (reg:DI 3 3 [ ps ])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3284:1 687 {*movdi_internal64} (expr_list:REG_DEAD (reg:DI 3 3 [ ps ]) (nil))) (insn 2 246 247 2 (set (reg/v/f:DI 161 [ ps ]) (reg:DI 213)) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3284:1 687 {*movdi_internal64} (expr_list:REG_DEAD (reg:DI 213) (nil))) (insn 247 2 3 2 (set (reg:DI 214) (reg:DI 4 4 [ start_cycle ])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3284:1 687 {*movdi_internal64} (expr_list:REG_DEAD (reg:DI 4 4 [ start_cycle ]) (nil))) (note 3 247 4 2 NOTE_INSN_DELETED) (note 4 3 8 2 NOTE_INSN_FUNCTION_BEG) (debug_insn 8 4 9 2 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3285:3 -1 (nil)) (debug_insn 9 8 10 2 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3286:3 -1 (nil)) (debug_insn 10 9 11 2 (var_location:SI D#61 (mem:SI (reg/v/f:DI 161 [ ps ]) [6 ps_33(D)->ii+0 S4 A64])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3286:22 -1 (nil)) (debug_insn 11 10 12 2 (var_location:SI last_row (plus:SI (debug_expr:SI D#61) (const_int -1 [0xffffffffffffffff]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3286:7 -1 (nil)) (debug_insn 12 11 13 2 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3288:3 -1 (nil)) (insn 13 12 14 2 (parallel [ (set (reg:CC 163) (compare:CC (reg:DI 214) (const_int 0 [0]))) (set (reg/v:DI 162 [ start_cycle ]) (reg:DI 214)) ]) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3288:3 566 {*movdi_internal2} (expr_list:REG_DEAD (reg:DI 214) (nil))) (jump_insn 14 13 15 2 (set (pc) (if_then_else (eq (reg:CC 163) (const_int 0 [0])) (label_ref:DI 160) (pc))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3288:3 930 {*cbranch} (expr_list:REG_DEAD (reg:CC 163) (int_list:REG_BR_PROB 365072228 (nil))) -> 160) ;; succ: 14 [34.0% (guessed)] count:7520214 (estimated locally) ;; 3 [66.0% (guessed)] count:14598063 (estimated locally) (FALLTHRU) ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 161 162 ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 161 162 ;; basic block 3, loop depth 0, count 14598063 (estimated locally), maybe hot ;; prev block 2, next block 4, flags: (REACHABLE, RTL, MODIFIED) ;; pred: 2 [66.0% (guessed)] count:14598063 (estimated locally) (FALLTHRU) ;; bb 3 artificial_defs: { } ;; bb 3 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 161 162 ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 161 162 ;; lr def 117 118 173 174 189 ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 161 162 ;; live gen 117 118 173 174 189 ;; live kill (note 15 14 16 3 [bb 3] NOTE_INSN_BASIC_BLOCK) (insn 16 15 17 3 (set (reg:SI 117 [ _1 ]) (mem:SI (reg/v/f:DI 161 [ ps ]) [6 ps_33(D)->ii+0 S4 A64])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3286:22 560 {*movsi_internal1} (nil)) (debug_insn 17 16 23 3 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3291:3 -1 (nil)) (insn 23 17 24 3 (set (reg:SI 173) (div:SI (subreg/s/u:SI (reg/v:DI 162 [ start_cycle ]) 0) (reg:SI 117 [ _1 ]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3291:22 184 {*divsi3} (nil)) (insn 24 23 25 3 (set (reg:SI 174) (mult:SI (reg:SI 173) (reg:SI 117 [ _1 ]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3291:22 159 {mulsi3} (expr_list:REG_DEAD (reg:SI 173) (nil))) (insn 25 24 28 3 (set (reg:SI 118 [ _2 ]) (minus:SI (subreg/s/u:SI (reg/v:DI 162 [ start_cycle ]) 0) (reg:SI 174))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3291:22 99 {*subfsi3} (expr_list:REG_DEAD (reg:SI 174) (nil))) (insn 28 25 29 3 (set (reg:CC 189) (compare:CC (reg:SI 118 [ _2 ]) (const_int 0 [0]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3291:22 844 {*cmpsi_signed} (nil)) (jump_insn 29 28 30 3 (set (pc) (if_then_else (ge (reg:CC 189) (const_int 0 [0])) (label_ref 32) (pc))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3291:22 930 {*cbranch} (int_list:REG_BR_PROB 633507684 (nil)) -> 32) ;; succ: 4 [41.0% (guessed)] count:5985206 (estimated locally) (FALLTHRU) ;; 5 [59.0% (guessed)] count:8612857 (estimated locally) ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 117 118 161 162 189 ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 117 118 161 162 189 ;; basic block 4, loop depth 0, count 5985206 (estimated locally), maybe hot ;; prev block 3, next block 5, flags: (REACHABLE, RTL, MODIFIED) ;; pred: 3 [41.0% (guessed)] count:5985206 (estimated locally) (FALLTHRU) ;; bb 4 artificial_defs: { } ;; bb 4 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 117 118 161 162 ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 117 118 ;; lr def 118 189 ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 117 118 161 162 ;; live gen 118 189 ;; live kill (note 30 29 31 4 [bb 4] NOTE_INSN_BASIC_BLOCK) (insn 31 30 168 4 (set (reg:SI 118 [ _2 ]) (plus:SI (reg:SI 118 [ _2 ]) (reg:SI 117 [ _1 ]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3291:22 discrim 1 68 {*addsi3} (nil)) (insn 168 31 32 4 (set (reg:CC 189) (compare:CC (reg:SI 118 [ _2 ]) (const_int 0 [0]))) 844 {*cmpsi_signed} (nil)) ;; succ: 5 [always] count:5985206 (estimated locally) (FALLTHRU) ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 117 118 161 162 189 ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 117 118 161 162 189 ;; basic block 5, loop depth 0, count 14598063 (estimated locally), maybe hot ;; prev block 4, next block 6, flags: (REACHABLE, RTL, MODIFIED) ;; pred: 4 [always] count:5985206 (estimated locally) (FALLTHRU) ;; 3 [59.0% (guessed)] count:8612857 (estimated locally) ;; bb 5 artificial_defs: { } ;; bb 5 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 117 118 161 162 189 ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 189 ;; lr def ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 117 118 161 162 189 ;; live gen ;; live kill (code_label 32 168 33 5 11 (nil) [1 uses]) (note 33 32 34 5 [bb 5] NOTE_INSN_BASIC_BLOCK) (debug_insn 34 33 35 5 (var_location:SI backward_rotates (reg:SI 118 [ _2 ])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3291:20 discrim 4 -1 (nil)) (debug_insn 35 34 36 5 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3294:3 -1 (nil)) (debug_insn 36 35 37 5 (var_location:SI i (const_int 0 [0])) -1 (nil)) (debug_insn 37 36 41 5 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3294:17 discrim 1 -1 (nil)) (jump_insn 41 37 42 5 (set (pc) (if_then_else (le (reg:CC 189) (const_int 0 [0])) (label_ref 148) (pc))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3294:17 discrim 1 930 {*cbranch} (expr_list:REG_DEAD (reg:CC 189) (int_list:REG_BR_PROB 118111604 (nil))) -> 148) ;; succ: 6 [89.0% (guessed)] count:12992276 (estimated locally) (FALLTHRU) ;; 13 [11.0% (guessed)] count:1605787 (estimated locally) ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 117 118 161 162 ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 117 118 161 162 ;; basic block 6, loop depth 0, count 12992276 (estimated locally), maybe hot ;; prev block 5, next block 7, flags: (REACHABLE, RTL, MODIFIED) ;; pred: 5 [89.0% (guessed)] count:12992276 (estimated locally) (FALLTHRU) ;; bb 6 artificial_defs: { } ;; bb 6 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 117 118 161 162 ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 117 161 ;; lr def 98 [ca] 119 120 128 129 130 131 132 137 139 143 146 147 150 151 152 153 154 158 177 178 179 180 181 182 183 190 191 192 193 194 195 ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 117 118 161 162 ;; live gen 98 [ca] 119 120 128 129 130 131 132 137 139 143 146 147 150 151 152 153 154 158 177 178 179 180 181 182 183 190 191 192 193 194 195 ;; live kill 98 [ca] (note 42 41 43 6 [bb 6] NOTE_INSN_BASIC_BLOCK) (insn 43 42 44 6 (set (reg:SI 190 [ _8 ]) (plus:SI (reg:SI 117 [ _1 ]) (const_int -1 [0xffffffffffffffff]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3286:7 68 {*addsi3} (nil)) (insn 44 43 45 6 (set (reg/f:DI 119 [ _3 ]) (mem/f:DI (plus:DI (reg/v/f:DI 161 [ ps ]) (const_int 8 [0x8])) [102 ps_33(D)->rows+0 S8 A64])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3296:35 687 {*movdi_internal64} (nil)) (insn 45 44 46 6 (set (reg/f:DI 120 [ _4 ]) (mem/f:DI (plus:DI (reg/v/f:DI 161 [ ps ]) (const_int 24 [0x18])) [104 ps_33(D)->rows_length+0 S8 A64])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3297:34 687 {*movdi_internal64} (nil)) (insn 46 45 47 6 (set (reg:DI 128 [ _17 ]) (sign_extend:DI (reg:SI 190 [ _8 ]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3305:16 34 {extendsidi2} (nil)) (insn 47 46 48 6 (set (reg:DI 129 [ _18 ]) (ashift:DI (reg:DI 128 [ _17 ]) (const_int 3 [0x3]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3305:24 283 {ashldi3} (nil)) (insn 48 47 49 6 (set (reg/f:DI 130 [ _19 ]) (plus:DI (reg/f:DI 119 [ _3 ]) (reg:DI 129 [ _18 ]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3305:24 69 {*adddi3} (expr_list:REG_DEAD (reg:DI 129 [ _18 ]) (nil))) (insn 49 48 50 6 (set (reg:DI 131 [ _20 ]) (ashift:DI (reg:DI 128 [ _17 ]) (const_int 2 [0x2]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3306:31 283 {ashldi3} (expr_list:REG_DEAD (reg:DI 128 [ _17 ]) (nil))) (insn 50 49 52 6 (set (reg/f:DI 132 [ _21 ]) (plus:DI (reg/f:DI 120 [ _4 ]) (reg:DI 131 [ _20 ]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3306:31 69 {*adddi3} (expr_list:REG_DEAD (reg:DI 131 [ _20 ]) (nil))) (insn 52 50 53 6 (set (reg:SI 154 [ _61 ]) (plus:SI (reg:SI 117 [ _1 ]) (const_int -2 [0xfffffffffffffffe]))) 68 {*addsi3} (expr_list:REG_DEAD (reg:SI 117 [ _1 ]) (nil))) (insn 53 52 54 6 (set (reg:DI 153 [ _60 ]) (zero_extend:DI (reg:SI 154 [ _61 ]))) 19 {zero_extendsidi2} (expr_list:REG_DEAD (reg:SI 154 [ _61 ]) (nil))) (insn 54 53 55 6 (set (reg:DI 152 [ _59 ]) (plus:DI (reg:DI 153 [ _60 ]) (const_int 2 [0x2]))) 69 {*adddi3} (nil)) (insn 55 54 56 6 (set (reg:DI 151 [ _58 ]) (ashift:DI (reg:DI 152 [ _59 ]) (const_int 3 [0x3]))) 283 {ashldi3} (expr_list:REG_DEAD (reg:DI 152 [ _59 ]) (nil))) (insn 56 55 57 6 (set (reg/f:DI 150 [ _57 ]) (plus:DI (reg/f:DI 119 [ _3 ]) (reg:DI 151 [ _58 ]))) 69 {*adddi3} (expr_list:REG_DEAD (reg:DI 151 [ _58 ]) (nil))) (insn 57 56 58 6 (parallel [ (set (reg:DI 178) (minus:DI (reg/f:DI 120 [ _4 ]) (reg/f:DI 150 [ _57 ]))) (set (reg:DI 98 ca) (leu:DI (reg/f:DI 150 [ _57 ]) (reg/f:DI 120 [ _4 ]))) ]) 109 {subfdi3_carry} (expr_list:REG_DEAD (reg/f:DI 150 [ _57 ]) (expr_list:REG_UNUSED (reg:DI 178) (nil)))) (insn 58 57 59 6 (parallel [ (set (reg:DI 179) (plus:DI (reg:DI 98 ca) (const_int -1 [0xffffffffffffffff]))) (clobber (reg:DI 98 ca)) ]) 119 {subfdi3_carry_in_xx} (expr_list:REG_DEAD (reg:DI 98 ca) (expr_list:REG_UNUSED (reg:DI 98 ca) (nil)))) (insn 59 58 61 6 (set (reg:DI 177) (plus:DI (reg:DI 179) (const_int 1 [0x1]))) 69 {*adddi3} (expr_list:REG_DEAD (reg:DI 179) (nil))) (insn 61 59 62 6 (set (reg:DI 147 [ _48 ]) (plus:DI (reg:DI 153 [ _60 ]) (const_int 1 [0x1]))) 69 {*adddi3} (expr_list:REG_DEAD (reg:DI 153 [ _60 ]) (nil))) (insn 62 61 63 6 (set (reg:DI 146 [ _47 ]) (ashift:DI (reg:DI 147 [ _48 ]) (const_int 2 [0x2]))) 283 {ashldi3} (nil)) (insn 63 62 64 6 (set (reg/f:DI 139 [ _30 ]) (plus:DI (reg/f:DI 120 [ _4 ]) (reg:DI 146 [ _47 ]))) 69 {*adddi3} (nil)) (insn 64 63 65 6 (parallel [ (set (reg:DI 181) (minus:DI (reg/f:DI 119 [ _3 ]) (reg/f:DI 139 [ _30 ]))) (set (reg:DI 98 ca) (leu:DI (reg/f:DI 139 [ _30 ]) (reg/f:DI 119 [ _3 ]))) ]) 109 {subfdi3_carry} (expr_list:REG_DEAD (reg/f:DI 139 [ _30 ]) (expr_list:REG_UNUSED (reg:DI 181) (nil)))) (insn 65 64 66 6 (parallel [ (set (reg:DI 182) (plus:DI (reg:DI 98 ca) (const_int -1 [0xffffffffffffffff]))) (clobber (reg:DI 98 ca)) ]) 119 {subfdi3_carry_in_xx} (expr_list:REG_DEAD (reg:DI 98 ca) (expr_list:REG_UNUSED (reg:DI 98 ca) (nil)))) (insn 66 65 68 6 (set (reg:SI 180) (reg:SI 98 ca)) 69 {*adddi3} (nil)) (insn 68 66 69 6 (set (reg:SI 183) (ior:SI (reg:SI 180) (subreg:SI (reg:DI 177) 0))) 226 {*boolsi3} (expr_list:REG_DEAD (reg:SI 180) (expr_list:REG_DEAD (reg:DI 177) (nil)))) (insn 69 68 70 6 (set (reg:QI 137 [ _27 ]) (subreg:QI (reg:SI 183) 0)) 567 {*movqi_internal} (expr_list:REG_DEAD (reg:SI 183) (nil))) (insn 70 69 5 6 (set (reg:DI 158 [ _84 ]) (ashift:DI (reg:DI 147 [ _48 ]) (const_int 3 [0x3]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3301:18 283 {ashldi3} (expr_list:REG_DEAD (reg:DI 147 [ _48 ]) (nil))) (insn 5 70 169 6 (set (reg/v:SI 143 [ i ]) (const_int 0 [0])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3294:10 560 {*movsi_internal1} (nil)) (insn 169 5 87 6 (set (reg:CC 191) (compare:CC (reg:SI 190 [ _8 ]) (const_int 0 [0]))) 844 {*cmpsi_signed} (nil)) (insn 87 169 88 6 (set (reg:SI 192 [ _27 ]) (zero_extend:SI (reg:QI 137 [ _27 ]))) 7 {zero_extendqisi2} (expr_list:REG_DEAD (reg:QI 137 [ _27 ]) (nil))) (insn 88 87 91 6 (set (reg:CC 193) (compare:CC (reg:SI 192 [ _27 ]) (const_int 0 [0]))) 844 {*cmpsi_signed} (expr_list:REG_DEAD (reg:SI 192 [ _27 ]) (nil))) (insn 91 88 96 6 (set (reg/f:DI 194 [ _85 ]) (plus:DI (reg/f:DI 119 [ _3 ]) (const_int 8 [0x8]))) 69 {*adddi3} (nil)) (insn 96 91 145 6 (set (reg/f:DI 195 [ _90 ]) (plus:DI (reg/f:DI 120 [ _4 ]) (const_int 4 [0x4]))) 69 {*adddi3} (nil)) ;; succ: 7 [always] count:12992276 (estimated locally) (FALLTHRU) ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 130 132 143 146 158 161 162 190 191 193 194 195 ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 119 120 130 132 143 146 158 161 162 190 191 193 194 195 ;; basic block 7, loop depth 0, count 118111600 (estimated locally), maybe hot ;; prev block 6, next block 8, flags: (REACHABLE, RTL, MODIFIED) ;; pred: 12 [89.0% (guessed)] count:105119324 (estimated locally) (DFS_BACK) ;; 6 [always] count:12992276 (estimated locally) (FALLTHRU) ;; bb 7 artificial_defs: { } ;; bb 7 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 130 132 143 146 158 161 162 190 191 193 194 195 ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 119 120 191 ;; lr def 141 142 ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 119 120 130 132 143 146 158 161 162 190 191 193 194 195 ;; live gen 141 142 ;; live kill (code_label 145 96 71 7 17 (nil) [1 uses]) (note 71 145 72 7 [bb 7] NOTE_INSN_BASIC_BLOCK) (debug_insn 72 71 73 7 (var_location:SI i (reg/v:SI 143 [ i ])) -1 (nil)) (debug_insn 73 72 74 7 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3296:7 -1 (nil)) (insn 74 73 75 7 (set (reg/v/f:DI 141 [ first_row ]) (mem/f:DI (reg/f:DI 119 [ _3 ]) [103 *_3+0 S8 A64])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3296:19 687 {*movdi_internal64} (nil)) (debug_insn 75 74 76 7 (var_location:DI first_row (reg/v/f:DI 141 [ first_row ])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3296:19 -1 (nil)) (debug_insn 76 75 77 7 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3297:7 -1 (nil)) (insn 77 76 78 7 (set (reg/v:SI 142 [ first_row_length ]) (mem:SI (reg/f:DI 120 [ _4 ]) [6 *_4+0 S4 A32])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3297:11 560 {*movsi_internal1} (nil)) (debug_insn 78 77 79 7 (var_location:SI first_row_length (reg/v:SI 142 [ first_row_length ])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3297:11 -1 (nil)) (debug_insn 79 78 80 7 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3299:7 -1 (nil)) (debug_insn 80 79 81 7 (var_location:SI row (const_int 0 [0])) -1 (nil)) (debug_insn 81 80 85 7 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3299:25 discrim 1 -1 (nil)) (jump_insn 85 81 86 7 (set (pc) (if_then_else (le (reg:CC 191) (const_int 0 [0])) (label_ref 135) (pc))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3299:25 discrim 1 930 {*cbranch} (int_list:REG_BR_PROB 118111604 (nil)) -> 135) ;; succ: 8 [89.0% (guessed)] count:105119324 (estimated locally) (FALLTHRU) ;; 12 [11.0% (guessed)] count:12992276 (estimated locally) ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 130 132 141 142 143 146 158 161 162 190 191 193 194 195 ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 119 120 130 132 141 142 143 146 158 161 162 190 191 193 194 195 ;; basic block 8, loop depth 0, count 105119324 (estimated locally), maybe hot ;; prev block 7, next block 9, flags: (REACHABLE, RTL, MODIFIED) ;; pred: 7 [89.0% (guessed)] count:105119324 (estimated locally) (FALLTHRU) ;; bb 8 artificial_defs: { } ;; bb 8 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 130 132 141 142 143 146 158 161 162 190 191 193 194 195 ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 193 ;; lr def ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 119 120 130 132 141 142 143 146 158 161 162 190 191 193 194 195 ;; live gen ;; live kill (note 86 85 89 8 [bb 8] NOTE_INSN_BASIC_BLOCK) (jump_insn 89 86 90 8 (set (pc) (if_then_else (eq (reg:CC 193) (const_int 0 [0])) (label_ref 103) (pc))) 930 {*cbranch} (int_list:REG_BR_PROB 107374188 (nil)) -> 103) ;; succ: 10 [10.0% (guessed)] count:10511933 (estimated locally) ;; 9 [90.0% (guessed)] count:94607391 (estimated locally) (FALLTHRU) ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 130 132 141 142 143 146 158 161 162 190 191 193 194 195 ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 119 120 130 132 141 142 143 146 158 161 162 190 191 193 194 195 ;; basic block 9, loop depth 0, count 94607391 (estimated locally), maybe hot ;; prev block 8, next block 10, flags: (REACHABLE, RTL, MODIFIED) ;; pred: 8 [90.0% (guessed)] count:94607391 (estimated locally) (FALLTHRU) ;; bb 9 artificial_defs: { } ;; bb 9 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 130 132 141 142 143 146 158 161 162 190 191 193 194 195 ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 119 120 146 158 194 195 ;; lr def 0 [0] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [0] 65 [1] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 78 [14] 79 [15] 80 [16] 81 [17] 82 [18] 83 [19] 96 [lr] 97 [ctr] 98 [ca] 100 [0] 101 [1] 105 [5] 106 [6] 107 [7] 109 [vscr] ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 119 120 130 132 141 142 143 146 158 161 162 190 191 193 194 195 ;; live gen 3 [3] 4 [4] 5 [5] 109 [vscr] ;; live kill 96 [lr] (note 90 89 92 9 [bb 9] NOTE_INSN_BASIC_BLOCK) (insn 92 90 93 9 (set (reg:DI 5 5) (reg:DI 158 [ _84 ])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3301:18 687 {*movdi_internal64} (nil)) (insn 93 92 94 9 (set (reg:DI 4 4) (reg/f:DI 194 [ _85 ])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3301:18 687 {*movdi_internal64} (nil)) (insn 94 93 95 9 (set (reg:DI 3 3) (reg/f:DI 119 [ _3 ])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3301:18 687 {*movdi_internal64} (nil)) (call_insn 95 94 97 9 (parallel [ (set (reg:DI 3 3) (call (mem:SI (symbol_ref:DI ("memmove") [flags 0x41] ) [0 __builtin_memmove S4 A8]) (const_int 0 [0]))) (use (const_int 0 [0])) (clobber (reg:DI 96 lr)) ]) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3301:18 810 {*call_value_nonlocal_aixdi} (expr_list:REG_DEAD (reg:DI 5 5) (expr_list:REG_DEAD (reg:DI 4 4) (expr_list:REG_UNUSED (reg:DI 3 3) (expr_list:REG_CALL_DECL (symbol_ref:DI ("memmove") [flags 0x41] ) (expr_list:REG_EH_REGION (const_int 0 [0]) (nil)))))) (expr_list (use (reg:DI 2 2)) (expr_list:DI (set (reg:DI 3 3) (reg:DI 3 3)) (expr_list:DI (use (reg:DI 3 3)) (expr_list:DI (use (reg:DI 4 4)) (expr_list:DI (use (reg:DI 5 5)) (nil))))))) (insn 97 95 98 9 (set (reg:DI 5 5) (reg:DI 146 [ _47 ])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3302:25 687 {*movdi_internal64} (nil)) (insn 98 97 99 9 (set (reg:DI 4 4) (reg/f:DI 195 [ _90 ])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3302:25 687 {*movdi_internal64} (nil)) (insn 99 98 100 9 (set (reg:DI 3 3) (reg/f:DI 120 [ _4 ])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3302:25 687 {*movdi_internal64} (nil)) (call_insn 100 99 103 9 (parallel [ (set (reg:DI 3 3) (call (mem:SI (symbol_ref:DI ("memmove") [flags 0x41] ) [0 __builtin_memmove S4 A8]) (const_int 0 [0]))) (use (const_int 0 [0])) (clobber (reg:DI 96 lr)) ]) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3302:25 810 {*call_value_nonlocal_aixdi} (expr_list:REG_DEAD (reg:DI 5 5) (expr_list:REG_DEAD (reg:DI 4 4) (expr_list:REG_UNUSED (reg:DI 3 3) (expr_list:REG_CALL_DECL (symbol_ref:DI ("memmove") [flags 0x41] ) (expr_list:REG_EH_REGION (const_int 0 [0]) (nil)))))) (expr_list (use (reg:DI 2 2)) (expr_list:DI (set (reg:DI 3 3) (reg:DI 3 3)) (expr_list:DI (use (reg:DI 3 3)) (expr_list:DI (use (reg:DI 4 4)) (expr_list:DI (use (reg:DI 5 5)) (nil))))))) ;; succ: 12 [always] count:94607391 (estimated locally) (FALLTHRU) ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 130 132 141 142 143 146 158 161 162 190 191 193 194 195 ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 119 120 130 132 141 142 143 146 158 161 162 190 191 193 194 195 ;; basic block 10, loop depth 0, count 10511933 (estimated locally), maybe hot ;; prev block 9, next block 11, flags: (NEW, REACHABLE, RTL, MODIFIED) ;; pred: 8 [10.0% (guessed)] count:10511933 (estimated locally) ;; bb 10 artificial_defs: { } ;; bb 10 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 130 132 141 142 143 146 158 161 162 190 191 193 194 195 ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 119 120 190 ;; lr def 121 123 124 196 197 198 199 ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 119 120 130 132 141 142 143 146 158 161 162 190 191 193 194 195 ;; live gen 121 123 124 196 197 198 199 ;; live kill (code_label 103 100 104 10 14 (nil) [1 uses]) (note 104 103 106 10 [bb 10] NOTE_INSN_BASIC_BLOCK) (insn 106 104 107 10 (set (reg:DI 123 [ doloop.995 ]) (zero_extend:DI (reg:SI 190 [ _8 ]))) 19 {zero_extendsidi2} (nil)) (insn 107 106 109 10 (set (reg:DI 121 [ ivtmp.998 ]) (plus:DI (reg/f:DI 119 [ _3 ]) (const_int -8 [0xfffffffffffffff8]))) 69 {*adddi3} (nil)) (insn 109 107 184 10 (set (reg:DI 124 [ ivtmp.1000 ]) (plus:DI (reg/f:DI 120 [ _4 ]) (const_int -4 [0xfffffffffffffffc]))) 69 {*adddi3} (nil)) (insn 184 109 185 10 (set (reg:DI 196) (plus:DI (reg:DI 123 [ doloop.995 ]) (const_int -1 [0xffffffffffffffff]))) 69 {*adddi3} (nil)) (insn 185 184 186 10 (set (reg:DI 197) (reg:DI 123 [ doloop.995 ])) 687 {*movdi_internal64} (nil)) (insn 186 185 211 10 (set (reg:DI 198) (and:DI (reg:DI 123 [ doloop.995 ]) (const_int 1 [0x1]))) 212 {anddi3_mask} (expr_list:REG_DEAD (reg:DI 123 [ doloop.995 ]) (nil))) (insn 211 186 212 10 (set (reg:CC 199) (compare:CC (reg:DI 198) (const_int 0 [0]))) 845 {*cmpdi_signed} (expr_list:REG_DEAD (reg:DI 198) (nil))) (jump_insn 212 211 129 10 (set (pc) (if_then_else (eq (reg:CC 199) (const_int 0 [0])) (label_ref:DI 210) (pc))) 930 {*cbranch} (expr_list:REG_DEAD (reg:CC 199) (int_list:REG_BR_PROB 536870918 (nil))) -> 210) ;; succ: 15 [50.0% (adjusted)] count:5255967 (estimated locally) (FALLTHRU) ;; 16 [50.0% (adjusted)] count:5255967 (estimated locally) ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 121 124 130 132 141 142 143 146 158 161 162 190 191 193 194 195 196 197 ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 119 120 121 124 130 132 141 142 143 146 158 161 162 190 191 193 194 195 196 197 ;; basic block 11, loop depth 0, count 42525546 (estimated locally), maybe hot ;; Invalid sum of incoming counts 47781514 (estimated locally), should be 42525546 (estimated locally) ;; prev block 10, next block 12, flags: (NEW, REACHABLE, RTL, MODIFIED) ;; pred: 16 [always] count:9933778 (estimated locally) (FALLTHRU) ;; 11 [89.0% (guessed)] count:37847736 (estimated locally) (DFS_BACK) ;; bb 11 artificial_defs: { } ;; bb 11 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 121 124 130 132 141 142 143 146 158 161 162 190 191 193 194 195 203 ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 121 124 203 ;; lr def 121 124 156 157 200 201 203 207 208 ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 119 120 121 124 130 132 141 142 143 146 158 161 162 190 191 193 194 195 203 ;; live gen 121 124 156 157 200 201 203 207 208 ;; live kill (code_label 129 212 111 11 16 (nil) [1 uses]) (note 111 129 112 11 [bb 11] NOTE_INSN_BASIC_BLOCK) (debug_insn 112 111 113 11 (var_location:SI row (clobber (const_int 0 [0]))) -1 (nil)) (debug_insn 113 112 115 11 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3301:4 -1 (nil)) (insn 115 113 234 11 (set (reg/f:DI 156 [ _72 ]) (mem/f:DI (plus:DI (reg:DI 121 [ ivtmp.998 ]) (const_int 16 [0x10])) [103 MEM[(struct ps_insn * *)_45 + 16B]+0 S8 A64])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3301:36 687 {*movdi_internal64} (nil)) (insn 234 115 118 11 (set (reg:DI 200) (plus:DI (reg:DI 121 [ ivtmp.998 ]) (const_int 8 [0x8]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3301:18 69 {*adddi3} (nil)) (insn 118 234 119 11 (set (mem/f:DI (plus:DI (reg:DI 121 [ ivtmp.998 ]) (const_int 8 [0x8])) [103 MEM[(struct ps_insn * *)_15]+0 S8 A64]) (reg/f:DI 156 [ _72 ])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3301:18 687 {*movdi_internal64} (expr_list:REG_DEAD (reg/f:DI 156 [ _72 ]) (expr_list:REG_DEAD (reg:DI 121 [ ivtmp.998 ]) (nil)))) (debug_insn 119 118 121 11 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3302:4 -1 (nil)) (insn 121 119 235 11 (set (reg:SI 157 [ _78 ]) (mem:SI (plus:DI (reg:DI 124 [ ivtmp.1000 ]) (const_int 8 [0x8])) [6 MEM[(int *)_46 + 8B]+0 S4 A32])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3302:50 560 {*movsi_internal1} (nil)) (insn 235 121 124 11 (set (reg:DI 201) (plus:DI (reg:DI 124 [ ivtmp.1000 ]) (const_int 4 [0x4]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3302:25 69 {*adddi3} (nil)) (insn 124 235 125 11 (set (mem:SI (plus:DI (reg:DI 124 [ ivtmp.1000 ]) (const_int 4 [0x4])) [6 MEM[(int *)_16]+0 S4 A32]) (reg:SI 157 [ _78 ])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3302:25 560 {*movsi_internal1} (expr_list:REG_DEAD (reg:SI 157 [ _78 ]) (expr_list:REG_DEAD (reg:DI 124 [ ivtmp.1000 ]) (nil)))) (debug_insn 125 124 126 11 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3299:7 discrim 3 -1 (nil)) (debug_insn 126 125 127 11 (var_location:SI row (clobber (const_int 0 [0]))) -1 (nil)) (debug_insn 127 126 215 11 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3299:25 discrim 1 -1 (nil)) (debug_insn 215 127 216 11 (var_location:SI row (clobber (const_int 0 [0]))) -1 (nil)) (debug_insn 216 215 217 11 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3301:4 -1 (nil)) (insn 217 216 218 11 (set (reg/f:DI 207 [ _72 ]) (mem/f:DI (plus:DI (reg:DI 200) (const_int 16 [0x10])) [103 MEM[(struct ps_insn * *)_45 + 16B]+0 S8 A64])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3301:36 687 {*movdi_internal64} (nil)) (insn 218 217 219 11 (set (reg:DI 121 [ ivtmp.998 ]) (plus:DI (reg:DI 200) (const_int 8 [0x8]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3301:18 69 {*adddi3} (nil)) (insn 219 218 220 11 (set (mem/f:DI (plus:DI (reg:DI 200) (const_int 8 [0x8])) [103 MEM[(struct ps_insn * *)_15]+0 S8 A64]) (reg/f:DI 207 [ _72 ])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3301:18 687 {*movdi_internal64} (expr_list:REG_DEAD (reg/f:DI 207 [ _72 ]) (expr_list:REG_DEAD (reg:DI 200) (nil)))) (debug_insn 220 219 221 11 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3302:4 -1 (nil)) (insn 221 220 222 11 (set (reg:SI 208 [ _78 ]) (mem:SI (plus:DI (reg:DI 201) (const_int 8 [0x8])) [6 MEM[(int *)_46 + 8B]+0 S4 A32])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3302:50 560 {*movsi_internal1} (nil)) (insn 222 221 223 11 (set (reg:DI 124 [ ivtmp.1000 ]) (plus:DI (reg:DI 201) (const_int 4 [0x4]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3302:25 69 {*adddi3} (nil)) (insn 223 222 224 11 (set (mem:SI (plus:DI (reg:DI 201) (const_int 4 [0x4])) [6 MEM[(int *)_16]+0 S4 A32]) (reg:SI 208 [ _78 ])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3302:25 560 {*movsi_internal1} (expr_list:REG_DEAD (reg:SI 208 [ _78 ]) (expr_list:REG_DEAD (reg:DI 201) (nil)))) (debug_insn 224 223 225 11 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3299:7 discrim 3 -1 (nil)) (debug_insn 225 224 226 11 (var_location:SI row (clobber (const_int 0 [0]))) -1 (nil)) (debug_insn 226 225 238 11 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3299:25 discrim 1 -1 (nil)) (jump_insn 238 226 135 11 (parallel [ (set (pc) (if_then_else (ne (reg:DI 203) (const_int 1 [0x1])) (label_ref:DI 129) (pc))) (set (reg:DI 203) (plus:DI (reg:DI 203) (const_int -1 [0xffffffffffffffff]))) (clobber (scratch:CC)) (clobber (scratch:DI)) ]) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3299:25 discrim 1 955 {bdnz_di} (int_list:REG_BR_PROB 955630228 (nil)) -> 129) ;; succ: 11 [89.0% (guessed)] count:37847736 (estimated locally) (DFS_BACK) ;; 12 [11.0% (guessed)] count:4677810 (estimated locally) (FALLTHRU,LOOP_EXIT) ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 121 124 130 132 141 142 143 146 158 161 162 190 191 193 194 195 203 ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 119 120 121 124 130 132 141 142 143 146 158 161 162 190 191 193 194 195 203 ;; basic block 12, loop depth 0, count 118111600 (estimated locally), maybe hot ;; Invalid sum of incoming counts 112855633 (estimated locally), should be 118111600 (estimated locally) ;; prev block 11, next block 13, flags: (REACHABLE, RTL, MODIFIED) ;; pred: 7 [11.0% (guessed)] count:12992276 (estimated locally) ;; 15 [11.0% (guessed)] count:578156 (estimated locally) (FALLTHRU,LOOP_EXIT) ;; 9 [always] count:94607391 (estimated locally) (FALLTHRU) ;; 11 [11.0% (guessed)] count:4677810 (estimated locally) (FALLTHRU,LOOP_EXIT) ;; bb 12 artificial_defs: { } ;; bb 12 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 130 132 141 142 143 146 158 161 162 190 191 193 194 195 ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 118 130 132 141 142 143 ;; lr def 143 188 ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 119 120 130 132 141 142 143 146 158 161 162 190 191 193 194 195 ;; live gen 143 188 ;; live kill (code_label 135 238 136 12 13 (nil) [1 uses]) (note 136 135 137 12 [bb 12] NOTE_INSN_BASIC_BLOCK) (debug_insn 137 136 138 12 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3305:7 -1 (nil)) (insn 138 137 139 12 (set (mem/f:DI (reg/f:DI 130 [ _19 ]) [103 *_19+0 S8 A64]) (reg/v/f:DI 141 [ first_row ])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3305:26 687 {*movdi_internal64} (expr_list:REG_DEAD (reg/v/f:DI 141 [ first_row ]) (nil))) (debug_insn 139 138 140 12 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3306:7 -1 (nil)) (insn 140 139 141 12 (set (mem:SI (reg/f:DI 132 [ _21 ]) [6 *_21+0 S4 A32]) (reg/v:SI 142 [ first_row_length ])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3306:33 560 {*movsi_internal1} (expr_list:REG_DEAD (reg/v:SI 142 [ first_row_length ]) (nil))) (debug_insn 141 140 142 12 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3294:3 discrim 2 -1 (nil)) (insn 142 141 143 12 (set (reg/v:SI 143 [ i ]) (plus:SI (reg/v:SI 143 [ i ]) (const_int 1 [0x1]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3294:3 discrim 2 68 {*addsi3} (nil)) (debug_insn 143 142 144 12 (var_location:SI i (reg/v:SI 143 [ i ])) -1 (nil)) (debug_insn 144 143 146 12 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3294:17 discrim 1 -1 (nil)) (insn 146 144 147 12 (set (reg:CC 188) (compare:CC (reg:SI 118 [ _2 ]) (reg/v:SI 143 [ i ]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3294:17 discrim 1 844 {*cmpsi_signed} (nil)) (jump_insn 147 146 148 12 (set (pc) (if_then_else (ne (reg:CC 188) (const_int 0 [0])) (label_ref:DI 145) (pc))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3294:17 discrim 1 930 {*cbranch} (expr_list:REG_DEAD (reg:CC 188) (int_list:REG_BR_PROB 955630228 (nil))) -> 145) ;; succ: 7 [89.0% (guessed)] count:105119324 (estimated locally) (DFS_BACK) ;; 13 [11.0% (guessed)] count:12992276 (estimated locally) (FALLTHRU,LOOP_EXIT) ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 130 132 143 146 158 161 162 190 191 193 194 195 ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 119 120 130 132 143 146 158 161 162 190 191 193 194 195 ;; basic block 13, loop depth 0, count 14598063 (estimated locally), maybe hot ;; prev block 12, next block 14, flags: (REACHABLE, RTL, MODIFIED) ;; pred: 5 [11.0% (guessed)] count:1605787 (estimated locally) ;; 12 [11.0% (guessed)] count:12992276 (estimated locally) (FALLTHRU,LOOP_EXIT) ;; bb 13 artificial_defs: { } ;; bb 13 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 161 162 ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 161 162 ;; lr def 133 134 135 136 ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 161 162 ;; live gen 133 134 135 136 ;; live kill (code_label 148 147 149 13 12 (nil) [1 uses]) (note 149 148 150 13 [bb 13] NOTE_INSN_BASIC_BLOCK) (debug_insn 150 149 151 13 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3309:3 -1 (nil)) (insn 151 150 152 13 (set (reg:SI 133 [ _22 ]) (mem:SI (plus:DI (reg/v/f:DI 161 [ ps ]) (const_int 36 [0x24])) [6 ps_33(D)->max_cycle+0 S4 A32])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3309:7 560 {*movsi_internal1} (nil)) (insn 152 151 153 13 (set (reg:SI 134 [ _23 ]) (minus:SI (reg:SI 133 [ _22 ]) (subreg/s/u:SI (reg/v:DI 162 [ start_cycle ]) 0))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3309:17 99 {*subfsi3} (expr_list:REG_DEAD (reg:SI 133 [ _22 ]) (nil))) (insn 153 152 154 13 (set (mem:SI (plus:DI (reg/v/f:DI 161 [ ps ]) (const_int 36 [0x24])) [6 ps_33(D)->max_cycle+0 S4 A32]) (reg:SI 134 [ _23 ])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3309:17 560 {*movsi_internal1} (expr_list:REG_DEAD (reg:SI 134 [ _23 ]) (nil))) (debug_insn 154 153 155 13 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3310:3 -1 (nil)) (insn 155 154 156 13 (set (reg:SI 135 [ _24 ]) (mem:SI (plus:DI (reg/v/f:DI 161 [ ps ]) (const_int 32 [0x20])) [6 ps_33(D)->min_cycle+0 S4 A64])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3310:7 560 {*movsi_internal1} (nil)) (insn 156 155 157 13 (set (reg:SI 136 [ _25 ]) (minus:SI (reg:SI 135 [ _24 ]) (subreg/s/u:SI (reg/v:DI 162 [ start_cycle ]) 0))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3310:17 99 {*subfsi3} (expr_list:REG_DEAD (reg/v:DI 162 [ start_cycle ]) (expr_list:REG_DEAD (reg:SI 135 [ _24 ]) (nil)))) (insn 157 156 160 13 (set (mem:SI (plus:DI (reg/v/f:DI 161 [ ps ]) (const_int 32 [0x20])) [6 ps_33(D)->min_cycle+0 S4 A64]) (reg:SI 136 [ _25 ])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3310:17 560 {*movsi_internal1} (expr_list:REG_DEAD (reg/v/f:DI 161 [ ps ]) (expr_list:REG_DEAD (reg:SI 136 [ _25 ]) (nil)))) ;; succ: 14 [always] count:14598063 (estimated locally) (FALLTHRU) ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] ;; basic block 14, loop depth 0, count 22118277 (estimated locally), maybe hot ;; prev block 13, next block 15, flags: (REACHABLE, RTL, MODIFIED) ;; pred: 13 [always] count:14598063 (estimated locally) (FALLTHRU) ;; 2 [34.0% (guessed)] count:7520214 (estimated locally) ;; bb 14 artificial_defs: { } ;; bb 14 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] ;; lr def ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] ;; live gen ;; live kill (code_label 160 157 161 14 9 (nil) [1 uses]) (note 161 160 205 14 [bb 14] NOTE_INSN_BASIC_BLOCK) ;; succ: EXIT [always] count:22118277 (estimated locally) (FALLTHRU) ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] ;; basic block 15, loop depth 0, count 5255967 (estimated locally), maybe hot ;; prev block 14, next block 16, flags: (REACHABLE, RTL, MODIFIED) ;; pred: 10 [50.0% (adjusted)] count:5255967 (estimated locally) (FALLTHRU) ;; bb 15 artificial_defs: { } ;; bb 15 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 121 124 130 132 141 142 143 146 158 161 162 190 191 193 194 195 196 197 ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 119 120 121 124 196 ;; lr def 121 123 124 210 211 212 ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 119 120 121 124 130 132 141 142 143 146 158 161 162 190 191 193 194 195 196 197 ;; live gen 121 123 124 210 211 212 ;; live kill (note 205 161 190 15 [bb 15] NOTE_INSN_BASIC_BLOCK) (debug_insn 190 205 191 15 (var_location:SI row (clobber (const_int 0 [0]))) -1 (nil)) (debug_insn 191 190 192 15 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3301:4 -1 (nil)) (insn 192 191 193 15 (set (reg/f:DI 210 [ _72 ]) (mem/f:DI (plus:DI (reg:DI 121 [ ivtmp.998 ]) (const_int 16 [0x10])) [103 MEM[(struct ps_insn * *)_45 + 16B]+0 S8 A64])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3301:36 687 {*movdi_internal64} (expr_list:REG_DEAD (reg:DI 121 [ ivtmp.998 ]) (nil))) (insn 193 192 194 15 (set (reg:DI 121 [ ivtmp.998 ]) (reg/f:DI 119 [ _3 ])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3301:18 687 {*movdi_internal64} (nil)) (insn 194 193 195 15 (set (mem/f:DI (reg/f:DI 119 [ _3 ]) [103 MEM[(struct ps_insn * *)_15]+0 S8 A64]) (reg/f:DI 210 [ _72 ])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3301:18 687 {*movdi_internal64} (expr_list:REG_DEAD (reg/f:DI 210 [ _72 ]) (nil))) (debug_insn 195 194 196 15 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3302:4 -1 (nil)) (insn 196 195 197 15 (set (reg:SI 211 [ _78 ]) (mem:SI (plus:DI (reg:DI 124 [ ivtmp.1000 ]) (const_int 8 [0x8])) [6 MEM[(int *)_46 + 8B]+0 S4 A32])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3302:50 560 {*movsi_internal1} (expr_list:REG_DEAD (reg:DI 124 [ ivtmp.1000 ]) (nil))) (insn 197 196 198 15 (set (reg:DI 124 [ ivtmp.1000 ]) (reg/f:DI 120 [ _4 ])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3302:25 687 {*movdi_internal64} (nil)) (insn 198 197 199 15 (set (mem:SI (reg/f:DI 120 [ _4 ]) [6 MEM[(int *)_16]+0 S4 A32]) (reg:SI 211 [ _78 ])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3302:25 560 {*movsi_internal1} (expr_list:REG_DEAD (reg:SI 211 [ _78 ]) (nil))) (debug_insn 199 198 200 15 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3299:7 discrim 3 -1 (nil)) (debug_insn 200 199 201 15 (var_location:SI row (clobber (const_int 0 [0]))) -1 (nil)) (debug_insn 201 200 202 15 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3299:25 discrim 1 -1 (nil)) (insn 202 201 203 15 (set (reg:DI 123 [ doloop.995 ]) (reg:DI 196)) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3299:25 discrim 1 687 {*movdi_internal64} (expr_list:REG_DEAD (reg:DI 196) (nil))) (insn 203 202 204 15 (set (reg:CC 212) (compare:CC (reg:DI 123 [ doloop.995 ]) (const_int 0 [0]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3299:25 discrim 1 845 {*cmpdi_signed} (expr_list:REG_DEAD (reg:DI 123 [ doloop.995 ]) (nil))) (jump_insn 204 203 210 15 (set (pc) (if_then_else (ne (reg:CC 212) (const_int 0 [0])) (label_ref:DI 210) (pc))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":3299:25 discrim 1 930 {*cbranch} (expr_list:REG_DEAD (reg:CC 212) (int_list:REG_BR_PROB 955630228 (nil))) -> 210) ;; succ: 16 [89.0% (guessed)] count:4677811 (estimated locally) ;; 12 [11.0% (guessed)] count:578156 (estimated locally) (FALLTHRU,LOOP_EXIT) ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 121 124 130 132 141 142 143 146 158 161 162 190 191 193 194 195 197 ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 119 120 121 124 130 132 141 142 143 146 158 161 162 190 191 193 194 195 197 ;; basic block 16, loop depth 0, count 9933778 (estimated locally), maybe hot ;; prev block 15, next block 1, flags: (NEW, REACHABLE, RTL, MODIFIED) ;; pred: 15 [89.0% (guessed)] count:4677811 (estimated locally) ;; 10 [50.0% (adjusted)] count:5255967 (estimated locally) ;; bb 16 artificial_defs: { } ;; bb 16 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }} ;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 121 124 130 132 141 142 143 146 158 161 162 190 191 193 194 195 197 ;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 197 ;; lr def 203 ;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 119 120 121 124 130 132 141 142 143 146 158 161 162 190 191 193 194 195 197 ;; live gen 203 ;; live kill (code_label 210 204 209 16 23 (nil) [2 uses]) (note 209 210 239 16 [bb 16] NOTE_INSN_BASIC_BLOCK) (insn 239 209 0 16 (set (reg:DI 203) (lshiftrt:DI (reg:DI 197) (const_int 1 [0x1]))) 293 {lshrdi3} (expr_list:REG_DEAD (reg:DI 197) (nil))) ;; succ: 11 [always] count:9933778 (estimated locally) (FALLTHRU) ;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 118 119 120 121 124 130 132 141 142 143 146 158 161 162 190 191 193 194 195 203 ;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 118 119 120 121 124 130 132 141 142 143 146 158 161 162 190 191 193 194 195 203