;; Function compute_jump_reg_dependencies (_ZL29compute_jump_reg_dependenciesP7rtx_defP11bitmap_head, funcdef_no=2456, decl_uid=99321, cgraph_uid=1504, symbol_order=1551) starting the processing of deferred insns ending the processing of deferred insns df_analyze called compute_jump_reg_dependencies Dataflow summary: ;; fully invalidated by EH 0 [0] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [0] 65 [1] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 78 [14] 79 [15] 80 [16] 81 [17] 82 [18] 83 [19] 96 [lr] 97 [ctr] 98 [ca] 100 [0] 101 [1] 105 [5] 106 [6] 107 [7] 109 [vscr] ;; hardware regs used 1 [1] 109 [vscr] ;; regular block artificial uses 1 [1] ;; eh block artificial uses 1 [1] 99 [ap] ;; entry block defs 1 [1] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 96 [lr] 109 [vscr] ;; exit block uses 1 [1] 2 [2] 96 [lr] 108 [vrsave] 109 [vscr] ;; regs ever live ;; ref usage r1={1d,2u} r2={1u} r3={1d} r4={1d} r5={1d} r6={1d} r7={1d} r8={1d} r9={1d} r10={1d} r33={1d} r34={1d} r35={1d} r36={1d} r37={1d} r38={1d} r39={1d} r40={1d} r41={1d} r42={1d} r43={1d} r44={1d} r45={1d} r66={1d} r67={1d} r68={1d} r69={1d} r70={1d} r71={1d} r72={1d} r73={1d} r74={1d} r75={1d} r76={1d} r77={1d} r96={1d,1u} r108={1u} r109={1d,1u} ;; total ref usage 42{36d,6u,0e} in 1{1 regular + 0 call} insns. ( )->[0]->( 2 ) ;; bb 0 artificial_defs: { d-1(1){ }d-1(3){ }d-1(4){ }d-1(5){ }d-1(6){ }d-1(7){ }d-1(8){ }d-1(9){ }d-1(10){ }d-1(33){ }d-1(34){ }d-1(35){ }d-1(36){ }d-1(37){ }d-1(38){ }d-1(39){ }d-1(40){ }d-1(41){ }d-1(42){ }d-1(43){ }d-1(44){ }d-1(45){ }d-1(66){ }d-1(67){ }d-1(68){ }d-1(69){ }d-1(70){ }d-1(71){ }d-1(72){ }d-1(73){ }d-1(74){ }d-1(75){ }d-1(76){ }d-1(77){ }d-1(96){ }d-1(109){ }} ;; bb 0 artificial_uses: { } ;; lr in 2 [2] 108 [vrsave] ;; lr use ;; lr def 1 [1] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 96 [lr] 109 [vscr] ;; live in ;; live gen 1 [1] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 96 [lr] 109 [vscr] ;; live kill ;; lr out 1 [1] 2 [2] 96 [lr] 108 [vrsave] 109 [vscr] ;; live out 1 [1] 96 [lr] 109 [vscr] ( 0 )->[2]->( 1 ) ;; bb 2 artificial_defs: { } ;; bb 2 artificial_uses: { u-1(1){ }} ;; lr in 1 [1] 2 [2] 96 [lr] 108 [vrsave] 109 [vscr] ;; lr use 1 [1] ;; lr def ;; live in 1 [1] 96 [lr] 109 [vscr] ;; live gen ;; live kill ;; lr out 1 [1] 2 [2] 96 [lr] 108 [vrsave] 109 [vscr] ;; live out 1 [1] 96 [lr] 109 [vscr] ( 2 )->[1]->( ) ;; bb 1 artificial_defs: { } ;; bb 1 artificial_uses: { u-1(1){ }u-1(2){ }u-1(96){ }u-1(108){ }u-1(109){ }} ;; lr in 1 [1] 2 [2] 96 [lr] 108 [vrsave] 109 [vscr] ;; lr use 1 [1] 2 [2] 96 [lr] 108 [vrsave] 109 [vscr] ;; lr def ;; live in 1 [1] 96 [lr] 109 [vscr] ;; live gen ;; live kill ;; lr out ;; live out Finding needed instructions: Adding insn 13 to worklist Finished finding needed instructions: processing block 2 lr out = 1 [1] 2 [2] 96 [lr] 108 [vrsave] 109 [vscr] starting the processing of deferred insns ending the processing of deferred insns compute_jump_reg_dependencies Dataflow summary: ;; fully invalidated by EH 0 [0] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [0] 65 [1] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 78 [14] 79 [15] 80 [16] 81 [17] 82 [18] 83 [19] 96 [lr] 97 [ctr] 98 [ca] 100 [0] 101 [1] 105 [5] 106 [6] 107 [7] 109 [vscr] ;; hardware regs used 1 [1] 109 [vscr] ;; regular block artificial uses 1 [1] ;; eh block artificial uses 1 [1] 99 [ap] ;; entry block defs 1 [1] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 96 [lr] 109 [vscr] ;; exit block uses 1 [1] 2 [2] 96 [lr] 108 [vrsave] 109 [vscr] ;; regs ever live ;; ref usage r1={1d,2u} r2={1u} r3={1d} r4={1d} r5={1d} r6={1d} r7={1d} r8={1d} r9={1d} r10={1d} r33={1d} r34={1d} r35={1d} r36={1d} r37={1d} r38={1d} r39={1d} r40={1d} r41={1d} r42={1d} r43={1d} r44={1d} r45={1d} r66={1d} r67={1d} r68={1d} r69={1d} r70={1d} r71={1d} r72={1d} r73={1d} r74={1d} r75={1d} r76={1d} r77={1d} r96={1d,1u} r108={1u} r109={1d,1u} ;; total ref usage 42{36d,6u,0e} in 1{1 regular + 0 call} insns. (note 1 0 5 NOTE_INSN_DELETED) ;; basic block 2, loop depth 0, count 1073741824 (estimated locally), maybe hot ;; prev block 0, next block 1, flags: (RTL) ;; pred: ENTRY [always] count:1073741824 (estimated locally) (FALLTHRU) ;; bb 2 artificial_defs: { } ;; bb 2 artificial_uses: { u-1(1){ }} ;; lr in 1 [1] 2 [2] 96 [lr] 108 [vrsave] 109 [vscr] ;; lr use 1 [1] ;; lr def ;; live in 1 [1] 96 [lr] 109 [vscr] ;; live gen ;; live kill (note 5 1 11 2 [bb 2] NOTE_INSN_BASIC_BLOCK) (note 11 5 4 2 NOTE_INSN_PROLOGUE_END) (note 4 11 12 2 NOTE_INSN_FUNCTION_BEG) (note 12 4 13 2 NOTE_INSN_EPILOGUE_BEG) (jump_insn 13 12 14 2 (simple_return) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":260:1 942 {simple_return} (nil) -> simple_return) ;; succ: EXIT [always] count:1073741824 (estimated locally) /builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc:260:1 ;; lr out 1 [1] 2 [2] 96 [lr] 108 [vrsave] 109 [vscr] ;; live out 1 [1] 96 [lr] 109 [vscr] (barrier 14 13 9) (note 9 14 10 NOTE_INSN_DELETED) (note 10 9 0 NOTE_INSN_DELETED) ;; Function update_node_sched_params (_ZL24update_node_sched_paramsiiii, funcdef_no=2466, decl_uid=99701, cgraph_uid=1514, symbol_order=1565) starting the processing of deferred insns ending the processing of deferred insns df_analyze called update_node_sched_params Dataflow summary: ;; fully invalidated by EH 0 [0] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [0] 65 [1] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 78 [14] 79 [15] 80 [16] 81 [17] 82 [18] 83 [19] 96 [lr] 97 [ctr] 98 [ca] 100 [0] 101 [1] 105 [5] 106 [6] 107 [7] 109 [vscr] ;; hardware regs used 1 [1] 109 [vscr] ;; regular block artificial uses 1 [1] ;; eh block artificial uses 1 [1] 99 [ap] ;; entry block defs 1 [1] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 96 [lr] 109 [vscr] ;; exit block uses 1 [1] 2 [2] 96 [lr] 108 [vrsave] 109 [vscr] ;; regs ever live 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 9 [9] 10 [10] 100 [0] ;; ref usage r1={1d,7u} r2={3u} r3={3d,6u} r4={1d,11u} r5={9d,15u} r6={4d,5u} r7={1d} r8={1d} r9={5d,6u} r10={3d,6u,1e} r33={1d} r34={1d} r35={1d} r36={1d} r37={1d} r38={1d} r39={1d} r40={1d} r41={1d} r42={1d} r43={1d} r44={1d} r45={1d} r66={1d} r67={1d} r68={1d} r69={1d} r70={1d} r71={1d} r72={1d} r73={1d} r74={1d} r75={1d} r76={1d} r77={1d} r96={1d,1u} r100={2d,2u} r108={1u} r109={1d,1u} ;; total ref usage 122{57d,64u,1e} in 60{60 regular + 0 call} insns. ( )->[0]->( 2 ) ;; bb 0 artificial_defs: { d-1(1){ }d-1(3){ }d-1(4){ }d-1(5){ }d-1(6){ }d-1(7){ }d-1(8){ }d-1(9){ }d-1(10){ }d-1(33){ }d-1(34){ }d-1(35){ }d-1(36){ }d-1(37){ }d-1(38){ }d-1(39){ }d-1(40){ }d-1(41){ }d-1(42){ }d-1(43){ }d-1(44){ }d-1(45){ }d-1(66){ }d-1(67){ }d-1(68){ }d-1(69){ }d-1(70){ }d-1(71){ }d-1(72){ }d-1(73){ }d-1(74){ }d-1(75){ }d-1(76){ }d-1(77){ }d-1(96){ }d-1(109){ }} ;; bb 0 artificial_uses: { } ;; lr in 2 [2] 108 [vrsave] ;; lr use ;; lr def 1 [1] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 96 [lr] 109 [vscr] ;; live in ;; live gen 1 [1] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 96 [lr] 109 [vscr] ;; live kill ;; lr out 1 [1] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 96 [lr] 108 [vrsave] 109 [vscr] ;; live out 1 [1] 3 [3] 4 [4] 5 [5] 6 [6] 96 [lr] 109 [vscr] ( 0 )->[2]->( 3 4 ) ;; bb 2 artificial_defs: { } ;; bb 2 artificial_uses: { u-1(1){ }} ;; lr in 1 [1] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 96 [lr] 108 [vrsave] 109 [vscr] ;; lr use 1 [1] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] ;; lr def 3 [3] 6 [6] 9 [9] 10 [10] 100 [0] ;; live in 1 [1] 3 [3] 4 [4] 5 [5] 6 [6] 96 [lr] 109 [vscr] ;; live gen 3 [3] 6 [6] 9 [9] 10 [10] 100 [0] ;; live kill ;; lr out 1 [1] 2 [2] 4 [4] 5 [5] 6 [6] 9 [9] 10 [10] 96 [lr] 108 [vrsave] 109 [vscr] ;; live out 1 [1] 4 [4] 5 [5] 6 [6] 9 [9] 10 [10] 96 [lr] 109 [vscr] ( 2 )->[3]->( 5 ) ;; bb 3 artificial_defs: { } ;; bb 3 artificial_uses: { u-1(1){ }} ;; lr in 1 [1] 2 [2] 4 [4] 5 [5] 6 [6] 9 [9] 10 [10] 96 [lr] 108 [vrsave] 109 [vscr] ;; lr use 1 [1] 4 [4] 9 [9] 10 [10] ;; lr def 9 [9] ;; live in 1 [1] 4 [4] 5 [5] 6 [6] 9 [9] 10 [10] 96 [lr] 109 [vscr] ;; live gen 9 [9] ;; live kill ;; lr out 1 [1] 2 [2] 4 [4] 5 [5] 6 [6] 10 [10] 96 [lr] 108 [vrsave] 109 [vscr] ;; live out 1 [1] 4 [4] 5 [5] 6 [6] 10 [10] 96 [lr] 109 [vscr] ( 2 )->[4]->( 5 6 ) ;; bb 4 artificial_defs: { } ;; bb 4 artificial_uses: { u-1(1){ }} ;; lr in 1 [1] 2 [2] 4 [4] 5 [5] 6 [6] 9 [9] 10 [10] 96 [lr] 108 [vrsave] 109 [vscr] ;; lr use 1 [1] 5 [5] 9 [9] 10 [10] ;; lr def 100 [0] ;; live in 1 [1] 4 [4] 5 [5] 6 [6] 9 [9] 10 [10] 96 [lr] 109 [vscr] ;; live gen 100 [0] ;; live kill ;; lr out 1 [1] 2 [2] 4 [4] 5 [5] 6 [6] 10 [10] 96 [lr] 108 [vrsave] 109 [vscr] ;; live out 1 [1] 4 [4] 5 [5] 6 [6] 10 [10] 96 [lr] 109 [vscr] ( 4 3 )->[5]->( 7 ) ;; bb 5 artificial_defs: { } ;; bb 5 artificial_uses: { u-1(1){ }} ;; lr in 1 [1] 2 [2] 4 [4] 5 [5] 6 [6] 10 [10] 96 [lr] 108 [vrsave] 109 [vscr] ;; lr use 1 [1] 4 [4] 5 [5] 6 [6] ;; lr def 5 [5] ;; live in 1 [1] 4 [4] 5 [5] 6 [6] 10 [10] 96 [lr] 109 [vscr] ;; live gen 5 [5] ;; live kill ;; lr out 1 [1] 2 [2] 5 [5] 10 [10] 96 [lr] 108 [vrsave] 109 [vscr] ;; live out 1 [1] 5 [5] 10 [10] 96 [lr] 109 [vscr] ( 4 )->[6]->( 7 ) ;; bb 6 artificial_defs: { } ;; bb 6 artificial_uses: { u-1(1){ }} ;; lr in 1 [1] 2 [2] 4 [4] 5 [5] 6 [6] 10 [10] 96 [lr] 108 [vrsave] 109 [vscr] ;; lr use 1 [1] 4 [4] 5 [5] 6 [6] ;; lr def 5 [5] ;; live in 1 [1] 4 [4] 5 [5] 6 [6] 10 [10] 96 [lr] 109 [vscr] ;; live gen 5 [5] ;; live kill ;; lr out 1 [1] 2 [2] 5 [5] 10 [10] 96 [lr] 108 [vrsave] 109 [vscr] ;; live out 1 [1] 5 [5] 10 [10] 96 [lr] 109 [vscr] ( 6 5 )->[7]->( 1 ) ;; bb 7 artificial_defs: { } ;; bb 7 artificial_uses: { u-1(1){ }} ;; lr in 1 [1] 2 [2] 5 [5] 10 [10] 96 [lr] 108 [vrsave] 109 [vscr] ;; lr use 1 [1] 5 [5] 10 [10] ;; lr def ;; live in 1 [1] 5 [5] 10 [10] 96 [lr] 109 [vscr] ;; live gen ;; live kill ;; lr out 1 [1] 2 [2] 96 [lr] 108 [vrsave] 109 [vscr] ;; live out 1 [1] 96 [lr] 109 [vscr] ( 7 )->[1]->( ) ;; bb 1 artificial_defs: { } ;; bb 1 artificial_uses: { u-1(1){ }u-1(2){ }u-1(96){ }u-1(108){ }u-1(109){ }} ;; lr in 1 [1] 2 [2] 96 [lr] 108 [vrsave] 109 [vscr] ;; lr use 1 [1] 2 [2] 96 [lr] 108 [vrsave] 109 [vscr] ;; lr def ;; live in 1 [1] 96 [lr] 109 [vscr] ;; live gen ;; live kill ;; lr out ;; live out Finding needed instructions: Adding insn 45 to worklist Adding insn 29 to worklist Adding insn 106 to worklist Adding insn 48 to worklist Adding insn 67 to worklist Adding insn 58 to worklist Adding insn 108 to worklist Adding insn 115 to worklist Adding insn 94 to worklist Finished finding needed instructions: processing block 7 lr out = 1 [1] 2 [2] 96 [lr] 108 [vrsave] 109 [vscr] processing block 5 lr out = 1 [1] 2 [2] 5 [5] 10 [10] 96 [lr] 108 [vrsave] 109 [vscr] Adding insn 77 to worklist Adding insn 74 to worklist Adding insn 72 to worklist Adding insn 71 to worklist processing block 3 lr out = 1 [1] 2 [2] 4 [4] 5 [5] 6 [6] 10 [10] 96 [lr] 108 [vrsave] 109 [vscr] Adding insn 47 to worklist processing block 6 lr out = 1 [1] 2 [2] 5 [5] 10 [10] 96 [lr] 108 [vrsave] 109 [vscr] Adding insn 91 to worklist Adding insn 90 to worklist Adding insn 87 to worklist Adding insn 85 to worklist processing block 4 lr out = 1 [1] 2 [2] 4 [4] 5 [5] 6 [6] 10 [10] 96 [lr] 108 [vrsave] 109 [vscr] Adding insn 66 to worklist processing block 2 lr out = 1 [1] 2 [2] 4 [4] 5 [5] 6 [6] 9 [9] 10 [10] 96 [lr] 108 [vrsave] 109 [vscr] Adding insn 44 to worklist Adding insn 37 to worklist Adding insn 24 to worklist Adding insn 36 to worklist Adding insn 41 to worklist Adding insn 39 to worklist Adding insn 38 to worklist Adding insn 23 to worklist Adding insn 22 to worklist Adding insn 35 to worklist Adding insn 117 to worklist starting the processing of deferred insns ending the processing of deferred insns update_node_sched_params Dataflow summary: ;; fully invalidated by EH 0 [0] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [0] 65 [1] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 78 [14] 79 [15] 80 [16] 81 [17] 82 [18] 83 [19] 96 [lr] 97 [ctr] 98 [ca] 100 [0] 101 [1] 105 [5] 106 [6] 107 [7] 109 [vscr] ;; hardware regs used 1 [1] 109 [vscr] ;; regular block artificial uses 1 [1] ;; eh block artificial uses 1 [1] 99 [ap] ;; entry block defs 1 [1] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 96 [lr] 109 [vscr] ;; exit block uses 1 [1] 2 [2] 96 [lr] 108 [vrsave] 109 [vscr] ;; regs ever live 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 9 [9] 10 [10] 100 [0] ;; ref usage r1={1d,7u} r2={3u} r3={3d,6u} r4={1d,11u} r5={9d,15u} r6={4d,5u} r7={1d} r8={1d} r9={5d,6u} r10={3d,6u,1e} r33={1d} r34={1d} r35={1d} r36={1d} r37={1d} r38={1d} r39={1d} r40={1d} r41={1d} r42={1d} r43={1d} r44={1d} r45={1d} r66={1d} r67={1d} r68={1d} r69={1d} r70={1d} r71={1d} r72={1d} r73={1d} r74={1d} r75={1d} r76={1d} r77={1d} r96={1d,1u} r100={2d,2u} r108={1u} r109={1d,1u} ;; total ref usage 122{57d,64u,1e} in 60{60 regular + 0 call} insns. (note 1 0 7 NOTE_INSN_DELETED) ;; basic block 2, loop depth 0, count 1073741824 (estimated locally), maybe hot ;; prev block 0, next block 3, flags: (RTL, MODIFIED) ;; pred: ENTRY [always] count:1073741824 (estimated locally) (FALLTHRU) ;; bb 2 artificial_defs: { } ;; bb 2 artificial_uses: { u-1(1){ }} ;; lr in 1 [1] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 96 [lr] 108 [vrsave] 109 [vscr] ;; lr use 1 [1] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] ;; lr def 3 [3] 6 [6] 9 [9] 10 [10] 100 [0] ;; live in 1 [1] 3 [3] 4 [4] 5 [5] 6 [6] 96 [lr] 109 [vscr] ;; live gen 3 [3] 6 [6] 9 [9] 10 [10] 100 [0] ;; live kill (note 7 1 113 2 [bb 2] NOTE_INSN_BASIC_BLOCK) (note 113 7 2 2 NOTE_INSN_PROLOGUE_END) (note 2 113 5 2 NOTE_INSN_DELETED) (note 5 2 6 2 NOTE_INSN_DELETED) (note 6 5 21 2 NOTE_INSN_FUNCTION_BEG) (note 21 6 9 2 NOTE_INSN_DELETED) (debug_insn 9 21 10 2 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":471:3 -1 (nil)) (debug_insn 10 9 11 2 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":472:3 -1 (nil)) (debug_insn 11 10 13 2 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":474:3 -1 (nil)) (debug_insn 13 11 117 2 (var_location:DI this (symbol_ref:DI ("_ZL20node_sched_param_vec") [flags 0x82] )) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":474:3 -1 (nil)) (insn 117 13 35 2 (set (reg/f:DI 10 10 [orig:131 _27 ] [131]) (unspec:DI [ (mem/f/c:DI (lo_sum:DI (high:DI (unspec:DI [ (symbol_ref:DI ("*.LANCHOR0") [flags 0x182]) (reg:DI 2 2) ] UNSPEC_TOCREL)) (unspec:DI [ (symbol_ref:DI ("*.LANCHOR0") [flags 0x182]) (reg:DI 2 2) ] UNSPEC_TOCREL)) [91 node_sched_param_vec.m_vec+0 S8 A64]) ] UNSPEC_FUSION_GPR)) "/builddir/gcc-13.2.1_git20231014/gcc/vec.h":1505:14 1010 {*fusion_gpr_load_di} (expr_list:REG_DEAD (reg:DI 2 2) (nil))) (insn 35 117 14 2 (set (reg:SI 9 9 [149]) (div:SI (reg:SI 5 5 [orig:139 cycle ] [139]) (reg:SI 4 4 [orig:138 ii ] [138]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":475:19 184 {*divsi3} (nil)) (debug_insn 14 35 15 2 (var_location:SI ix (reg:SI 3 3 [157])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":474:3 -1 (nil)) (debug_insn 15 14 18 2 (debug_marker:BLK) "/builddir/gcc-13.2.1_git20231014/gcc/vec.h":1504:6 -1 (nil)) (debug_insn 18 15 19 2 (var_location:DI this (reg/f:DI 10 10 [orig:131 _27 ] [131])) "/builddir/gcc-13.2.1_git20231014/gcc/vec.h":1505:14 -1 (nil)) (debug_insn 19 18 20 2 (var_location:SI ix (reg:SI 3 3 [157])) "/builddir/gcc-13.2.1_git20231014/gcc/vec.h":1505:14 -1 (nil)) (debug_insn 20 19 22 2 (debug_marker:BLK) "/builddir/gcc-13.2.1_git20231014/gcc/vec.h":888:1 -1 (nil)) (insn 22 20 23 2 (set (reg:DI 3 3 [orig:135 _31 ] [135]) (and:DI (ashift:DI (reg:DI 3 3 [157]) (const_int 4 [0x4])) (const_int 68719476720 [0xffffffff0]))) "/builddir/gcc-13.2.1_git20231014/gcc/vec.h":891:20 discrim 1 247 {*rotldi3_mask} (nil)) (insn 23 22 38 2 (set (reg:DI 3 3 [orig:133 _29 ] [133]) (plus:DI (reg:DI 3 3 [orig:135 _31 ] [135]) (const_int 8 [0x8]))) 69 {*adddi3} (nil)) (insn 38 23 39 2 (set (reg:SI 6 6 [orig:126 _13 ] [126]) (minus:SI (reg:SI 4 4 [orig:138 ii ] [138]) (reg:SI 6 6 [160]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":479:25 99 {*subfsi3} (nil)) (insn 39 38 29 2 (set (reg:SI 6 6 [orig:132 _28 ] [132]) (plus:SI (reg:SI 6 6 [orig:126 _13 ] [126]) (const_int -1 [0xffffffffffffffff]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":479:25 68 {*addsi3} (nil)) (insn 29 39 41 2 (set (mem:SI (plus:DI (reg/f:DI 10 10 [orig:131 _27 ] [131]) (reg:DI 3 3 [orig:133 _29 ] [133])) [6 _24->time+0 S4 A32]) (reg:SI 5 5 [orig:139 cycle ] [139])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":474:18 discrim 1 560 {*movsi_internal1} (nil)) (insn 41 29 36 2 (set (reg:SI 6 6 [orig:136 _32 ] [136]) (div:SI (reg:SI 6 6 [orig:132 _28 ] [132]) (reg:SI 4 4 [orig:138 ii ] [138]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":479:23 184 {*divsi3} (nil)) (insn 36 41 24 2 (set (reg:SI 9 9 [151]) (mult:SI (reg:SI 9 9 [149]) (reg:SI 4 4 [orig:138 ii ] [138]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":475:19 159 {mulsi3} (nil)) (insn 24 36 25 2 (set (reg/f:DI 10 10 [orig:128 _24 ] [128]) (plus:DI (reg/f:DI 10 10 [orig:131 _27 ] [131]) (reg:DI 3 3 [orig:133 _29 ] [133]))) "/builddir/gcc-13.2.1_git20231014/gcc/vec.h":891:23 discrim 1 69 {*adddi3} (expr_list:REG_DEAD (reg:DI 3 3 [orig:133 _29 ] [133]) (nil))) (debug_insn 25 24 26 2 (var_location:DI this (clobber (const_int 0 [0]))) "/builddir/gcc-13.2.1_git20231014/gcc/vec.h":1505:20 -1 (nil)) (debug_insn 26 25 27 2 (var_location:SI ix (clobber (const_int 0 [0]))) "/builddir/gcc-13.2.1_git20231014/gcc/vec.h":1505:20 -1 (nil)) (debug_insn 27 26 28 2 (var_location:DI this (clobber (const_int 0 [0]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":474:3 -1 (nil)) (debug_insn 28 27 30 2 (var_location:SI ix (clobber (const_int 0 [0]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":474:3 -1 (nil)) (debug_insn 30 28 37 2 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":475:3 -1 (nil)) (insn 37 30 44 2 (set (reg:SI 9 9 [orig:118 _2 ] [118]) (minus:SI (reg:SI 5 5 [orig:139 cycle ] [139]) (reg:SI 9 9 [151]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":475:19 99 {*subfsi3} (nil)) (insn 44 37 45 2 (set (reg:CC 100 0 [153]) (compare:CC (reg:SI 9 9 [orig:118 _2 ] [118]) (const_int 0 [0]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":475:19 844 {*cmpsi_signed} (nil)) (jump_insn 45 44 46 2 (set (pc) (if_then_else (ge (reg:CC 100 0 [153]) (const_int 0 [0])) (label_ref 56) (pc))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":475:19 930 {*cbranch} (expr_list:REG_DEAD (reg:CC 100 0 [153]) (int_list:REG_BR_PROB 633507684 (nil))) -> 56) ;; succ: 3 [41.0% (guessed)] count:440234144 (estimated locally) (FALLTHRU) ;; 4 [59.0% (guessed)] count:633507680 (estimated locally) ;; lr out 1 [1] 2 [2] 4 [4] 5 [5] 6 [6] 9 [9] 10 [10] 96 [lr] 108 [vrsave] 109 [vscr] ;; live out 1 [1] 4 [4] 5 [5] 6 [6] 9 [9] 10 [10] 96 [lr] 109 [vscr] ;; basic block 3, loop depth 0, count 440234144 (estimated locally), maybe hot ;; prev block 2, next block 4, flags: (RTL) ;; pred: 2 [41.0% (guessed)] count:440234144 (estimated locally) (FALLTHRU) ;; bb 3 artificial_defs: { } ;; bb 3 artificial_uses: { u-1(1){ }} ;; lr in 1 [1] 2 [2] 4 [4] 5 [5] 6 [6] 9 [9] 10 [10] 96 [lr] 108 [vrsave] 109 [vscr] ;; lr use 1 [1] 4 [4] 9 [9] 10 [10] ;; lr def 9 [9] ;; live in 1 [1] 4 [4] 5 [5] 6 [6] 9 [9] 10 [10] 96 [lr] 109 [vscr] ;; live gen 9 [9] ;; live kill (note 46 45 47 3 [bb 3] NOTE_INSN_BASIC_BLOCK) (insn 47 46 48 3 (set (reg:SI 9 9 [orig:127 iftmp.521_20 ] [127]) (plus:SI (reg:SI 9 9 [orig:118 _2 ] [118]) (reg:SI 4 4 [orig:138 ii ] [138]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":475:19 discrim 1 68 {*addsi3} (expr_list:REG_EQUIV (mem:SI (plus:DI (reg/f:DI 10 10 [orig:128 _24 ] [128]) (const_int 4 [0x4])) [6 _24->row+0 S4 A32]) (nil))) (insn 48 47 49 3 (set (mem:SI (plus:DI (reg/f:DI 10 10 [orig:128 _24 ] [128]) (const_int 4 [0x4])) [6 _24->row+0 S4 A32]) (reg:SI 9 9 [orig:127 iftmp.521_20 ] [127])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":475:17 discrim 1 560 {*movsi_internal1} (expr_list:REG_DEAD (reg:SI 9 9 [orig:127 iftmp.521_20 ] [127]) (nil))) (debug_insn 49 48 50 3 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":479:3 -1 (nil)) (debug_insn 50 49 51 3 (var_location:SI D#58 (clobber (const_int 0 [0]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":479:25 -1 (nil)) (debug_insn 51 50 52 3 (var_location:SI D#57 (plus:SI (debug_expr:SI D#58) (const_int -1 [0xffffffffffffffff]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":479:25 -1 (nil)) (debug_insn 52 51 53 3 (var_location:SI sc_until_cycle_zero (div:SI (debug_expr:SI D#57) (reg:SI 4 4 [orig:138 ii ] [138]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":479:23 -1 (nil)) (debug_insn 53 52 106 3 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":481:3 -1 (nil)) (jump_insn 106 53 107 3 (set (pc) (label_ref 68)) 940 {jump} (nil) -> 68) ;; succ: 5 [always] count:440234144 (estimated locally) ;; lr out 1 [1] 2 [2] 4 [4] 5 [5] 6 [6] 10 [10] 96 [lr] 108 [vrsave] 109 [vscr] ;; live out 1 [1] 4 [4] 5 [5] 6 [6] 10 [10] 96 [lr] 109 [vscr] (barrier 107 106 56) ;; basic block 4, loop depth 0, count 633507680 (estimated locally), maybe hot ;; prev block 3, next block 5, flags: (RTL) ;; pred: 2 [59.0% (guessed)] count:633507680 (estimated locally) ;; bb 4 artificial_defs: { } ;; bb 4 artificial_uses: { u-1(1){ }} ;; lr in 1 [1] 2 [2] 4 [4] 5 [5] 6 [6] 9 [9] 10 [10] 96 [lr] 108 [vrsave] 109 [vscr] ;; lr use 1 [1] 5 [5] 9 [9] 10 [10] ;; lr def 100 [0] ;; live in 1 [1] 4 [4] 5 [5] 6 [6] 9 [9] 10 [10] 96 [lr] 109 [vscr] ;; live gen 100 [0] ;; live kill (code_label 56 107 57 4 4 (nil) [1 uses]) (note 57 56 66 4 [bb 4] NOTE_INSN_BASIC_BLOCK) (insn 66 57 58 4 (set (reg:CC 100 0 [154]) (compare:CC (reg:SI 5 5 [orig:139 cycle ] [139]) (const_int 0 [0]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":481:3 discrim 1 844 {*cmpsi_signed} (nil)) (insn 58 66 59 4 (set (mem:SI (plus:DI (reg/f:DI 10 10 [orig:128 _24 ] [128]) (const_int 4 [0x4])) [6 _24->row+0 S4 A32]) (reg:SI 9 9 [orig:118 _2 ] [118])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":475:17 discrim 1 560 {*movsi_internal1} (expr_list:REG_DEAD (reg:SI 9 9 [orig:118 _2 ] [118]) (nil))) (debug_insn 59 58 60 4 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":479:3 -1 (nil)) (debug_insn 60 59 61 4 (var_location:SI D#60 (clobber (const_int 0 [0]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":479:25 -1 (nil)) (debug_insn 61 60 62 4 (var_location:SI D#59 (plus:SI (debug_expr:SI D#60) (const_int -1 [0xffffffffffffffff]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":479:25 -1 (nil)) (debug_insn 62 61 63 4 (var_location:SI sc_until_cycle_zero (div:SI (debug_expr:SI D#59) (reg:SI 4 4 [orig:138 ii ] [138]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":479:23 -1 (nil)) (debug_insn 63 62 67 4 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":481:3 -1 (nil)) (jump_insn 67 63 68 4 (set (pc) (if_then_else (ge (reg:CC 100 0 [154]) (const_int 0 [0])) (label_ref 80) (pc))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":481:3 discrim 1 930 {*cbranch} (expr_list:REG_DEAD (reg:CC 100 0 [154]) (int_list:REG_BR_PROB 914812532 (nil))) -> 80) ;; succ: 5 [14.8% (guessed)] count:93768285 (estimated locally) (FALLTHRU) ;; 6 [85.2% (guessed)] count:539739395 (estimated locally) ;; lr out 1 [1] 2 [2] 4 [4] 5 [5] 6 [6] 10 [10] 96 [lr] 108 [vrsave] 109 [vscr] ;; live out 1 [1] 4 [4] 5 [5] 6 [6] 10 [10] 96 [lr] 109 [vscr] ;; basic block 5, loop depth 0, count 440234144 (estimated locally), maybe hot ;; Invalid sum of incoming counts 534002429 (estimated locally), should be 440234144 (estimated locally) ;; prev block 4, next block 6, flags: (RTL) ;; pred: 4 [14.8% (guessed)] count:93768285 (estimated locally) (FALLTHRU) ;; 3 [always] count:440234144 (estimated locally) ;; bb 5 artificial_defs: { } ;; bb 5 artificial_uses: { u-1(1){ }} ;; lr in 1 [1] 2 [2] 4 [4] 5 [5] 6 [6] 10 [10] 96 [lr] 108 [vrsave] 109 [vscr] ;; lr use 1 [1] 4 [4] 5 [5] 6 [6] ;; lr def 5 [5] ;; live in 1 [1] 4 [4] 5 [5] 6 [6] 10 [10] 96 [lr] 109 [vscr] ;; live gen 5 [5] ;; live kill (code_label 68 67 69 5 5 (nil) [1 uses]) (note 69 68 70 5 [bb 5] NOTE_INSN_BASIC_BLOCK) (debug_insn 70 69 71 5 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":483:7 -1 (nil)) (insn 71 70 72 5 (set (reg:SI 5 5 [orig:119 _5 ] [119]) (minus:SI (reg:SI 4 4 [orig:138 ii ] [138]) (reg:SI 5 5 [orig:139 cycle ] [139]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":483:15 discrim 1 99 {*subfsi3} (nil)) (insn 72 71 74 5 (set (reg:SI 5 5 [orig:120 _6 ] [120]) (plus:SI (reg:SI 5 5 [orig:119 _5 ] [119]) (const_int -1 [0xffffffffffffffff]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":483:15 discrim 1 68 {*addsi3} (nil)) (insn 74 72 75 5 (set (reg/v:SI 5 5 [orig:134 stage ] [134]) (div:SI (reg:SI 5 5 [orig:120 _6 ] [120]) (reg:SI 4 4 [orig:138 ii ] [138]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":483:13 discrim 1 184 {*divsi3} (expr_list:REG_DEAD (reg:SI 4 4 [orig:138 ii ] [138]) (nil))) (debug_insn 75 74 76 5 (var_location:SI stage (reg/v:SI 5 5 [orig:134 stage ] [134])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":483:13 discrim 1 -1 (nil)) (debug_insn 76 75 77 5 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":484:7 -1 (nil)) (insn 77 76 108 5 (set (reg:SI 5 5 [orig:125 _12 ] [125]) (minus:SI (reg:SI 6 6 [orig:136 _32 ] [136]) (reg/v:SI 5 5 [orig:134 stage ] [134]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":484:45 99 {*subfsi3} (expr_list:REG_DEAD (reg:SI 6 6 [orig:136 _32 ] [136]) (nil))) (jump_insn 108 77 109 5 (set (pc) (label_ref 92)) 940 {jump} (nil) -> 92) ;; succ: 7 [always] count:440234144 (estimated locally) ;; lr out 1 [1] 2 [2] 5 [5] 10 [10] 96 [lr] 108 [vrsave] 109 [vscr] ;; live out 1 [1] 5 [5] 10 [10] 96 [lr] 109 [vscr] (barrier 109 108 80) ;; basic block 6, loop depth 0, count 633507681 (estimated locally), maybe hot ;; Invalid sum of incoming counts 539739395 (estimated locally), should be 633507681 (estimated locally) ;; prev block 5, next block 7, flags: (RTL) ;; pred: 4 [85.2% (guessed)] count:539739395 (estimated locally) ;; bb 6 artificial_defs: { } ;; bb 6 artificial_uses: { u-1(1){ }} ;; lr in 1 [1] 2 [2] 4 [4] 5 [5] 6 [6] 10 [10] 96 [lr] 108 [vrsave] 109 [vscr] ;; lr use 1 [1] 4 [4] 5 [5] 6 [6] ;; lr def 5 [5] ;; live in 1 [1] 4 [4] 5 [5] 6 [6] 10 [10] 96 [lr] 109 [vscr] ;; live gen 5 [5] ;; live kill (code_label 80 109 81 6 6 (nil) [1 uses]) (note 81 80 83 6 [bb 6] NOTE_INSN_BASIC_BLOCK) (note 83 81 84 6 NOTE_INSN_DELETED) (note 84 83 82 6 NOTE_INSN_DELETED) (debug_insn 82 84 85 6 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":488:7 -1 (nil)) (insn 85 82 87 6 (set (reg:SI 5 5 [orig:123 _10 ] [123]) (plus:SI (reg:SI 5 5 [orig:139 cycle ] [139]) (reg:SI 4 4 [orig:138 ii ] [138]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":488:15 discrim 1 68 {*addsi3} (nil)) (insn 87 85 88 6 (set (reg/v:SI 5 5 [orig:130 stage ] [130]) (div:SI (reg:SI 5 5 [orig:123 _10 ] [123]) (reg:SI 4 4 [orig:138 ii ] [138]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":488:13 discrim 1 184 {*divsi3} (expr_list:REG_DEAD (reg:SI 4 4 [orig:138 ii ] [138]) (nil))) (debug_insn 88 87 89 6 (var_location:SI stage (reg/v:SI 5 5 [orig:130 stage ] [130])) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":488:13 discrim 1 -1 (nil)) (debug_insn 89 88 90 6 (debug_marker) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":489:7 -1 (nil)) (insn 90 89 91 6 (set (reg:SI 5 5 [orig:124 _11 ] [124]) (plus:SI (reg/v:SI 5 5 [orig:130 stage ] [130]) (reg:SI 6 6 [orig:136 _32 ] [136]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":489:45 68 {*addsi3} (expr_list:REG_DEAD (reg:SI 6 6 [orig:136 _32 ] [136]) (nil))) (insn 91 90 92 6 (set (reg:SI 5 5 [orig:125 _12 ] [125]) (plus:SI (reg:SI 5 5 [orig:124 _11 ] [124]) (const_int -1 [0xffffffffffffffff]))) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":489:53 68 {*addsi3} (nil)) ;; succ: 7 [always] count:633507681 (estimated locally) (FALLTHRU) ;; lr out 1 [1] 2 [2] 5 [5] 10 [10] 96 [lr] 108 [vrsave] 109 [vscr] ;; live out 1 [1] 5 [5] 10 [10] 96 [lr] 109 [vscr] ;; basic block 7, loop depth 0, count 1073741824 (estimated locally), maybe hot ;; prev block 6, next block 1, flags: (RTL) ;; pred: 6 [always] count:633507681 (estimated locally) (FALLTHRU) ;; 5 [always] count:440234144 (estimated locally) ;; bb 7 artificial_defs: { } ;; bb 7 artificial_uses: { u-1(1){ }} ;; lr in 1 [1] 2 [2] 5 [5] 10 [10] 96 [lr] 108 [vrsave] 109 [vscr] ;; lr use 1 [1] 5 [5] 10 [10] ;; lr def ;; live in 1 [1] 5 [5] 10 [10] 96 [lr] 109 [vscr] ;; live gen ;; live kill (code_label 92 91 93 7 7 (nil) [1 uses]) (note 93 92 94 7 [bb 7] NOTE_INSN_BASIC_BLOCK) (insn 94 93 114 7 (set (mem:SI (plus:DI (reg/f:DI 10 10 [orig:128 _24 ] [128]) (const_int 8 [0x8])) [6 _24->stage+0 S4 A32]) (reg:SI 5 5 [orig:125 _12 ] [125])) 560 {*movsi_internal1} (expr_list:REG_DEAD (reg/f:DI 10 10 [orig:128 _24 ] [128]) (expr_list:REG_DEAD (reg:SI 5 5 [orig:125 _12 ] [125]) (nil)))) (note 114 94 115 7 NOTE_INSN_EPILOGUE_BEG) (jump_insn 115 114 116 7 (simple_return) "/builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc":491:1 942 {simple_return} (nil) -> simple_return) ;; succ: EXIT [always] count:1073741824 (estimated locally) /builddir/gcc-13.2.1_git20231014/gcc/modulo-sched.cc:491:1 ;; lr out 1 [1] 2 [2] 96 [lr] 108 [vrsave] 109 [vscr] ;; live out 1 [1] 96 [lr] 109 [vscr] (barrier 116 115 110) (note 110 116 111 NOTE_INSN_DELETED) (note 111 110 0 NOTE_INSN_DELETED)